High-memory capacity DIMM with data and state memory

Claim 2

A dual in-line memory module (DEI) comprising: a circuit board having a connector; first memory means for storing data, wherein said first memory means includes at least one semiconductor memory chip mounted on said circuit board, said at least one semiconductor memory chip is coupled to said connector by a first data path and a first address path; and second memory means for storing directory information, wherein said second memory means includes at least one further semiconductor memory chip mounted on said circuit board and said at least one further semiconductor memory chip is coupled to said connector by a second data path and a second address path;, wherein said first and second data paths and said first and second address paths permit said first memory means and said second memory means to be accessed separately.

Claim 3

The DIMM of claim 1, wherein said second memory means stores directory information corresponding to at least a portion of said data.

Claim 4

The DIMM of claim 1, wherein said connector comprises: a first group of address pads coupled to said first address path, a second group of address pads coupled to said second address path, a first group of data pads coupled to said first data path, and a second group of data pads coupled to said second data path.

Claim 5

The DIMM of claim 3, wherein said connector further comprises: a first set of control pads for said first memory means, and a second set of control pads for said second memory means.

Claim 6

The DIMM of claim 4, wherein each of said first and second sets of control pads include row access strobe pads, column access strobe pads, chip enable pads and write enable pads.

Claim 7

The DIMM of claim 3, wherein said first group of address pads includes at least 12 pads.

Claim 8

The DIMM of claim 3, wherein said second group of address pads includes at least 12 pads.

Claim 9

The DIMM of claim 3, wherein said first group of data pads includes at least 72 pads.

Claim 10

The DIMM of claim 3, wherein said second group of data pads includes at least 16 pads.

Claim 11

The DIMM of claim 3, wherein said connector is an edge connector having two sides and at least 122 pads per side.

Claim 12

The DIMM of claim 4, wherein said first memory means and said second memory means each comprise a plurality of synchronous dynamic random access memory (SDRAM) chips.

Claim 13

The DIMM of claim 11, wherein said first memory means is divided into a first memory bank portion of SDRAM chips and a second memory bank portion of SDRAM chips.

Claim 14

The DIMM of claim 12, wherein said first memory bank portion and said second memory bank portion each comprises at least nine (9) SDRAM chips.

Claim 15

The DIMM of claim 13, wherein each of said at least nine (9) SDRAM chips is two megabits (2M) deep and eight (8) bits wide.

Claim 16

The DIMM of claim 14, wherein said second memory means comprises at least one one megabit (1M) deep by sixteen (16) bit wide SDRAM chip.

Claim 17

The DIMM of claim 12, wherein said first memory bank portion and said second memory bank portion each comprise at least eighteen (18) SDRAM chips.

Claim 18

The DIMM of claim 16, wherein each of said at least eighteen (18) SDRAM chips is four megabits (4M) deep and four (4) bits wide.

Claim 19

The DIMM of claim 17, wherein said second memory means comprises at least two two megabit (2M) deep by eight (8) bit wide SDRAM chips.

Claim 20

The DIMM of claim 18, wherein said printed circuit board comprises a first circuit board supporting a second circuit board in a parallel, piggy back configuration.

Claim 21

The DIMM of claim 16, wherein each of said at least eighteen (18) SDRAM chips is sixteen megabits (16M) deep and four (4) bits wide, and said first group of address pads includes at least 14 pads.

Claim 22

The DIMM of claim 20, wherein said second memory means comprises at least two eight (8M) deep by eight (8) bit wide SDRAM chips.

Claim 23

The DIMM of claim 1, wherein said first memory means and said second memory means each comprise a plurality of dynamic random access memory (DRAM) chips.

Claim 24

The DIMM of claim 1, further comprising a phase locked loop clock driver coupled to said first and second memory means.

Claim 25

The DIMM of claim 1, further comprising a buffer for buffering address and control signals for said first memory means.

Claim 26

The DIMM of claim 1, further comprising a programmable read only memory to store information identifying the DIMM.

Claim 27

The DIMM of claim 1, wherein said first memory means is logically organized into memory blocks, and said second memory means is configured for storing information about where data stored in a group of said memory blocks is cached.

Claim 28

The DIMM of claim 1, wherein said first memory means is logically organized into memory blocks, and said second memory means is configured for storing access rights for the data stored in a group of said memory blocks.

Claim 29

The DIMM of claim 1, wherein said first memory means is logically organized into memory blocks, and said second memory means is configured for storing cache state information about data stored in a group of said memory blocks.

Claim 30

A dual in-line memory module (DIMM) comprising: a circuit board having a connector; and a plurality of semiconductor memory chips mounted on said circuit board and organized into a first memory bank portion and a second memory bank portion, wherein said first memory bank portion is coupled to said connector via a first data path and a first address path, and said second memory bank portion is coupled to said connector via a second data path and a second address path so that said first and second memory bank portions are separately addressable.

Claim 31

A dual in-line memory module (DIMM) comprising: a circuit board having a connector; and a plurality of semiconductor memory chips mounted on said circuit board and organized into a first memory bank portion and a second memory bank portion, wherein said first memory bank portion is coupled to said connector via a first data path and a first address path, and said second memory bank portion is coupled to said connector via a second data path and a second address path so that said first and second memory bank portions are separately addressable.

Claim 32

The DIMM of claim 29, wherein said connector comprises a plurality of pads, said pads including a first group of address pads, a second group of address pads, a first group of data pads, and a second group of data pads.

Claim 33

The DIMM of claim 30, wherein said plurality of pads has the following arrangement: said first group of data pads and said first group of address pads are electrically coupled to said data memory; and said second group of data pads and said second group of address pads are electrically coupled to said state memory, wherein said arrangement permits independent addressing of said data memory and said state memory.

Claim 34

The DIMM of claim 31, wherein said data memory and said state memory each comprise a plurality of synchronous dynamic random access memory (SDRAM) chips.

Claim 35

The DIMM of claim 32, wherein said data memory is divided into a first memory bank portion of SDRAM chips and a second memory bank portion of SDRAM chips.

Claim 36

The DIMM of claim 33, wherein said first memory bank portion and said second memory bank portion each comprise at least nine (9) SDRAM chips.

Claim 37

The DIMM of claim 34, wherein each of said at least nine (9) SDRAM chips is two megabits (2M) deep and eight (8) bits wide.

Claim 38

The DIMM of claim 35, wherein said state memory comprises at least one one megabit (1M) deep by sixteen (16) bit wide SDRAM chip.

Claim 39

The DIMM of claim 33, wherein said first memory bank portion and said second memory bank portion each comprise at least eighteen (18) SDRAM chips.

Claim 40

The DIMM of claim 37, wherein each of said at least eighteen (18) SDRAM chips is four megabits (4M) deep and four (4) bits wide.

Claim 41

The DIMM of claim 38, wherein said state memory comprises at least two two megabit (2M) deep by eight (8) bit wide SDRAM chips.

Claim 42

The DIMM of claim 39, wherein said printed circuit board comprises a first circuit board supporting a second circuit board in a parallel, piggy back configuration.

Claim 43

The DIMM of claim 37, wherein each of said at least eighteen (18) SDRAM chips is sixteen megabits (16M) deep and four (4) bits wide, and said first group of address pads includes 14 pads.

Claim 44

The DIMM of claim 41, wherein said state memory comprises at least two eight megabit (8M) deep by eight (8) bit wide SDRAM chips.

Claim 45

The DIMM of claim 30, wherein said plurality of pads further comprises separate control pads for said data memory and said state memory.

Claim 46

The DIMM of claim 43, wherein said control pads include row access strobe pads, column access strobe pads, chip enable pads and write enable pads.

Claim 47

The DIMM of claim 30, wherein said first group of address pads includes at least 12 pads.

Claim 48

The DIMM of claim 30, wherein said second group of address pads includes at least 12 pads.

Claim 49

The DIMM of claim 30, wherein said first group of data pads includes at least 72 pads.

Claim 50

The DIMM of claim 30, wherein said second group of data pads includes at least 16 pads.

Claim 51

The DIMM of claim 30, wherein said connector is an edge connector having two sides and at least 122 pads per side.

Claim 52

The DIMM of claim 29, wherein said plurality of semiconductor memory chips are mounted directly on said circuit board.

Claim 53

The DIMM of claim 29, wherein said first memory bank portion is organized into memory blocks for storing data and said second memory bank portion stores directory information for said memory blocks of said first memory bank portion.

Claim 54

The DIMM of claim 51, said second memory bank portion is configured to store said directory information to indicate, on a memory block-by-memory block basis, whether data stored in a group of said memory blocks has been cached.

Claim 55

The DIMM of claim 22, wherein said second memory bank portion is further configured to store said directory information to indicate, on said memory block-by-memory block basis, where data stored in a group of said memory blocks has been cached.

Claim 56

A dual in-line memory module (DIMM) comprising: a circuit board; a data memory mounted on said circuit board; a state memory mounted on said circuit board; and a connector coupled to said data memory and said state memory to permit independent addressing of said data memory and said state memory, said connector comprising a plurality of pads, including a first group of address pads, a second group of address pads, a first group of data pads, and a second group of data pads; wherein said first group of data pads and said first group of address pads are electrically coupled to said data memory and said second group of data pads and said second group of address pads are electrically coupled to said state memory to permit said data memory and said state memory to be accessed separately; wherein said connector is an edge connector having two sides and at least 122 pads per side, said first group of address pads including at least 12 pads, said second group of address pads including at least 12 pads, said first group of data pads including at least 72 pads, and said second group of data pads including at least 16 pads; wherein said data memory and said state memory each comprise a plurality of dynamic random access memory (DRAM) chips, and said data memory is divided into a first memory bank portion of DRAM chips and a second memory bank portion of DRAM chips, and said first memory bank portion and said second memory bank portion each comprise at least nine (9) DRAM chips, and said state memory comprises at least one megabit (1M) deep by sixteen (16) bit wide DRAM chip.

Claim 57

A dual in-line memory module (DIMM) comprising: a circuit board; a data memory mounted on said circuit board; a state memory mounted on said circuit board; and a connector coupled to said data memory and said state memory to permit independent addressing of said data memory and said state memory, said connector comprising a plurality of pads, including a first group of address pads, a second group of address pads, a first group of data pads, and a second group of data pads; wherein said first group of data pads and said first group of address pads are electrically coupled to said data memory and said second group of data pads and said second group of address pads are electrically coupled to said state memory to permit said data memory and said state memory to be accessed separately; wherein said connector is an edge connector having two sides and at least 122 pads per side, said first group of address pads including at least 12 pads, said second group of address pads including at least 12 pads, said first group of data pads including at least 72 pads, and said second group of data pads including at least 16 pads; wherein said data memory and said state memory each comprise a plurality of dynamic random access memory (DRAM) chips, and said data memory is divided into a first memory bank portion of DRAM chips and a second memory bank portion of DRAM chips, and said first memory bank portion and said second memory bank portion each comprise at least nine (9) DRAM chips, and said state memory comprises at least one megabit (1M) deep by sixteen (16) bit wide DRAM chip.

Claim 58

The DIMM of claim 54, wherein said data memory is logically organized into memory blocks, and said state memory stores information about where data stored in a group of said memory blocks is cached.

Claim 59

The DIMM of claim 54, wherein said data memory is logically organized into memory blocks, and said state memory stores access rights for the data stored in a group of said memory blocks.

Claim 60

The DIMM of claim 54, wherein said data memory is logically organized into memory blocks, and said state memory stores cache state information about data stored in a group of said memory blocks.

Claim 61

The DIM of claim 54, wherein said data memory and said state memory each comprise a plurality of synchronous dynamic random access memory (SDRAM) chips.

Claim 62

The DIMM of claim 58, wherein each of said at least nine (9) SDRAM chips is two megabits (2M) deep and eight (8) bits wide.

Claim 63

The DIMM of claim 58, wherein said first memory bank portion and said second memory bank portion each comprise at least eighteen (18) SDRAM chips.

Claim 64

The DIMM of claim 60, wherein each of said at least eighteen (18) SDRAM chips is four megabits (4M) deep and four (4) bits wide.

Claim 65

The DIMM of claim 61, wherein said state memory comprises at least two two megabit (2M) deep by eight (8) bit wide SDRAM chips.

Claim 66

The DIMM of claim 60, wherein each of said at least eighteen (18) SDRAM chips is sixteen megabits (16M) deep and four (4) bits wide, and said first group of address pads includes 14 pads.

Claim 67

The DIMM of claim 60, wherein said state memory comprises at least two eight megabit (8M) deep by eight (8) bit wide SDRAM chips.

Claim 68

The DIMM of claim 54, wherein said DRAM chips are mounted directly on said circuit board.

Claim 69

A dual in-line memory module (DIMM) comprising: a circuit board; a data memory mounted on said circuit board; a state memory mounted on said circuit board, said state memory being separate and distinct from said data memory; and means for permitting independent and simultaneous access of said data memory and said state memory so that different operations to different locations of said data memory and said state memory can be done in parallel.

Claim 70

A dual in-line memory module (DIMM) comprising: a circuit board; a data memory mounted on said circuit board; a state memory mounted on said circuit board, said state memory being separate and distinct from said data memory; and means for permitting independent and simultaneous access of said data memory and said state memory so that different operations to different locations of said data memory and said state memory can be done in parallel.

Claim 71

The DIMM of claim 66, wherein said means comprises a connector and first and second sets of busses on said circuit board.

Claim 72

The DIMM of claim 67, wherein said connector comprises a plurality of pads, said pads including: a first group of address pads, a second group of address pads, a first group of data pads, and a second group of data pads.

Claim 73

The DIMM of claim 68, wherein said plurality of pads has the following arrangement: said first group of data pads and said first group of address pads are electrically coupled via said first set of busses to said data memory; and said second group of data pads and said second group of address pads are electrically coupled via said second set of buses to said state memory.

Claim 74

The DIMM of claim 66, wherein said data memory and said state memory each comprise a plurality of dynamic random access memory (DRAM) chips.

Claim 75

The DIMM of claim 66, further comprising a phase locked loop clock driver coupled to said data memory and said state memory.

Claim 76

The DIMM of claim 66, further comprising a buffer for buffering address and control signals for said data memory.

Claim 77

The DIMM of claim 66, further comprising a programmable read only memory to store information identifying the DIMM.

Claim 78

The DIMM of claim 66, wherein said data memory is logically organized into memory blocks, and said state memory is configured for storing information about where data stored in a group of said memory blocks is cached.

Claim 79

The DIMM of claim 66, wherein said data memory is logically organized into memory blocks, and said state memory is configured for storing access rights for the data stored in a group of said memory blocks.

Claim 80

The DIMM of claim 66, wherein said data memory is logically organized into memory blocks, and said state memory is configured for storing cache state information about data stored in a group of said memory blocks.