Structure and method for loading RAM data within a programmable logic device

Claim 3

The method of claim 1, wherein configuration information for said first circuit, the data, and configuration information for said second circuit are combined to form a single data stream which is input to the programmable logic device.

Claim 4

The method of claim 1, wherein the memory block is comprised of a plurality of memory elements.

Claim 5

The method of claim 1, wherein the programmable logic device is a field programmable gate array (FPGA).

Claim 6

The method of claim 1, wherein the programmable logic device is a partially reconfigurable field programmable gate array (FPGA).

Claim 7

The method of claim 1, wherein input lines to the programmable logic device function as input lines for loading said data through said first circuit.

Claim 8

The method of claim 1, wherein the method further comprises the steps of: receiving said data in a resister means in the first circuit and forwarding said data to said RAM block; writing said data to a predetermined position within said RAM block using an addressing means; controlling said register means and said addressing means.

Claim 9

A computer-implemented system for loading data into a volatile memory block located within a programmable logic device, the system comprising: means for forwarding a first configuration bitstream from a data storage unit to the programmable logic device to thereby initially configure the programmable logic device as a first circuit capable of loading the data into the volatile memory block; means for supplying the data from the data storage unit to the programmable logic device configured as the first circuit for loading the data into the volatile memory block; and means for forwarding a second configuration bitstream from said data storage unit to the programmable logic device to thereby reconfigure the programmable logic device as a second circuit.

Claim 10

A computer-implemented system for loading data into a volatile memory block located within a programmable logic device, the system comprising: means for forwarding a first configuration bitstream from a data storage unit to the programmable logic device to thereby initially configure the programmable logic device as a first circuit capable of loading the data into the volatile memory block; means for supplying the data from the data storage unit to the programmable logic device configured as the first circuit for loading the data into the volatile memory block; and means for forwarding a second configuration bitstream from said data storage unit to the programmable logic device to thereby reconfigure the programmable logic device as a second circuit.

Claim 11

The computer-implemented system of claim 8, wherein said second circuit utilizes said data stored in the volatile memory block.

Claim 12

The computer-implemented system of claim 8, wherein said first and said second configuration bitstreams are combined with said data to form a consolidated bitstream.

Claim 13

The computer-implemented system of claim 8, wherein the volatile memory block is comprised of a plurality of dedicated memory elements.

Claim 14

The computer-implemented system of claim 8, wherein the programmable logic device is a field programmable gate array (FPGA).

Claim 15

The computer-implemented system of claim 8, wherein the programmable logic device is a partially reconfigurable field programmable gate array (FPGA).

Claim 16

The computer-implemented system of claim 8, wherein input lines to the programmable logic device function as input lines for loading said data through said first circuit.

Claim 17

The computer-implemented system of claim 8, wherein said first circuit comprises: register means for receiving said data and forwarding said data to said memory; addressing means for writing said data to a predetermined position within said memory; and control means for controlling said register means and said addressing means.