US5640107A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for in-circuit programming of a field-programmable gate array configuration memory
Assignee: Northrop Grumman Systems Corp
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Filing: 1995-10-24
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Granted: 1997-06-17
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Expires: 2015-10-24
Abstract
Abstract A programmable logic circuit includes a non-volatile, in-circuit programmable FPGA memory containing configuration data for programming an FPGA to perform one or more desired logic functions. The chips in the circuit may be packaged individually or may be mounted in die form on a multichip module. A method for programming an FPGA memory includes the steps of downloading a first set of data into an FPGA to program the FPGA to function as an FPGA memory programmer, and then downloading a second set of data into the FPGA, the second set of data being of a type for programming the FPGA to perform one or more logic functions. The second set of data, however, is not immediately loaded into the FPGA but instead is programmed into the FPGA memory in a manner controlled by the programming function of the FPGA. A method for programming an FPGA includes as a step the aforementioned method. A multichip module contains an FPGA die and FPGA memory die, either of which may be programmed in accordance with the methods described above.
Inventors
- 👤 Neils A. Kruse
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:34
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/34; H; H10; H10W; H10W90/00; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
149 words
A method for programming a memory with data, to be subsequently used to program an FPGA to perform a desired function, while said memory and FPGA are situated in circuit, said FPGA containing an internal storage means for storing data for altering functioning of the FPGA, and being adapted to communicate with said memory and with an external means, comprising the steps of: downloading, from said external means, a first set of data into the internal storage means of said FPGA, said first set of data configuring the FPGA to function as a programmer for programming said memory; downloading, from said external means, a second set of data into said FPGA, said second set of data being a type for configuring said FPGA to perform said desired function; and programming said memory with said second set of data in a manner controlled by the programming function of said FPGA.
Claim 2
Independent Claim
149 words
A method for programming a memory with data, to be subsequently used to program an FPGA to perform a desired function, while said memory and FPGA are situated in circuit, said FPGA containing an internal storage means for storing data for altering functioning of the FPGA, and being adapted to communicate with said memory and with an external means, comprising the steps of: downloading, from said external means, a first set of data into the internal storage means of said FPGA, said first set of data configuring the FPGA to function as a programmer for programming said memory; downloading, from said external means, a second set of data into said FPGA, said second set of data being a type for configuring said FPGA to perform said desired function; and programming said memory with said second set of data in a manner controlled by the programming function of said FPGA.
Claim 3
Dependent Claim
43 words
A method as defined in claim 1, further comprising: selecting said memory to be of a type which is non-volatile, so that said second set of data programmed into said memory will be retained therein after power to said memory is turned off.
Claim 4
Dependent Claim
22 words
A method as defined in claim 2, wherein said non-volatile memory is selected from a group consisting of EEPROM, EPROM, and PROM.
Claim 5
Dependent Claim
24 words
A method as defined in claim 1, further comprising: reprogramming said memory by repeating the preceding steps with a different second set of data.
Claim 6
Dependent Claim
15 words
A method as recited in claim 1, wherein said external means is a microprocessor-based system.
Claim 7
Dependent Claim
22 words
A method as defined in claim 1, wherein the FPGA and memory are bare integrated circuit dies incorporated within an MCM package.
Claim 8
Independent Claim
204 words
A method for programming an FPGA while in circuit to perform a desired function, said FPGA containing an internal volatile storage means for receiving therein data for altering functioning of the FPGA, said method comprising the steps of: providing a non-volatile memory in circuit with said FPGA; supplying power to the FPGA and memory; downloading, from an external source, a first set of data into the internal storage means of said FPGA, said first set of data configuring the FPGA to function as a programmer for programming said memory; downloading, from the external source, a second set of data into said FPGA, said second set of data being a type for configuring said FPGA to perform said desired function; programming said memory with said second set of data in a manner controlled by the programming function of said FPGA; removing power from the FPGA and memory, thereby causing the first set of data to become erased from the internal storage means of the FPGA; and re-supplying the FPGA and memory with power, to thereby cause the second set of data within said memory to be automatically loaded into the internal storage means of the FPGA to program the FPGA to perform the desired function.
Claim 9
Independent Claim
204 words
A method for programming an FPGA while in circuit to perform a desired function, said FPGA containing an internal volatile storage means for receiving therein data for altering functioning of the FPGA, said method comprising the steps of: providing a non-volatile memory in circuit with said FPGA; supplying power to the FPGA and memory; downloading, from an external source, a first set of data into the internal storage means of said FPGA, said first set of data configuring the FPGA to function as a programmer for programming said memory; downloading, from the external source, a second set of data into said FPGA, said second set of data being a type for configuring said FPGA to perform said desired function; programming said memory with said second set of data in a manner controlled by the programming function of said FPGA; removing power from the FPGA and memory, thereby causing the first set of data to become erased from the internal storage means of the FPGA; and re-supplying the FPGA and memory with power, to thereby cause the second set of data within said memory to be automatically loaded into the internal storage means of the FPGA to program the FPGA to perform the desired function.
Claim 10
Dependent Claim
21 words
A method as recited in claim 7, wherein said memory is selected from a group consisting of EEPROM, EPROM, and PROM.
Claim 11
Dependent Claim
27 words
A method as recited in claim 7, further comprising the step of: reprogramming the FPGA by repeating the preceding steps with a different second set of data.
Claim 12
Dependent Claim
15 words
A method as defined in claim 7, wherein said external source is a microprocessor-based system.
Claim 13
Dependent Claim
43 words
A method as defined in claim 7, further comprising: connecting an interface between the FPGA and the external source, said interface being used to transfer said first and second sets of data from said source into the internal storage means of said FPGA.
Claim 14
Dependent Claim
24 words
A method as defined in claim 7, wherein the FPGA and the non-volatile memory are bare integrated circuit dies incorporated within an MCM package.
Claim 15
Dependent Claim
79 words
A programmable logic circuit for performing a desired function comprising: an FPGA connected to an external source for receiving a first set of data to configure the FPGA as a programmer for an FPGA memory, and for receiving a second set of data for transfer to the FPGA memory under control of said FPGA configured as an FPGA memory programmer, said second set of data being subsequently used to configure the FPGA so as to perform a desired function.
Claim 16
Dependent Claim
79 words
A programmable logic circuit for performing a desired function comprising: an FPGA connected to an external source for receiving a first set of data to configure the FPGA as a programmer for an FPGA memory, and for receiving a second set of data for transfer to the FPGA memory under control of said FPGA configured as an FPGA memory programmer, said second set of data being subsequently used to configure the FPGA so as to perform a desired function.
Claim 17
Dependent Claim
19 words
A programmable logic circuit according to claim 13, wherein said FPGA memory is a non-volatile, in circuit programmable memory.
Claim 18
Dependent Claim
79 words
A programmable logic circuit for performing a desired function comprising: an FPGA and an FPGA memory; means for entering programming data to the FPGA so as to function as an FPGA memory programmer; means for entering configuration data into the FPGA memory; means for erasing the programming data from the FPGA; and means for loading the configuration data from the FPGA memory to the FPGA to program the FPGA so as to perform at least one desired system function.
Claim 19
Dependent Claim
79 words
A programmable logic circuit for performing a desired function comprising: an FPGA and an FPGA memory; means for entering programming data to the FPGA so as to function as an FPGA memory programmer; means for entering configuration data into the FPGA memory; means for erasing the programming data from the FPGA; and means for loading the configuration data from the FPGA memory to the FPGA to program the FPGA so as to perform at least one desired system function.
Claim 20
Dependent Claim
19 words
A programmable logic circuit according to claim 15, wherein said FPGA memory is a non-volatile, in circuit programmable memory.
References Cited (Backward Citations)
US5271887A
Cited
US4870302A
Cited
US4780846A
Cited
US5440453A
Cited
US5432708A
Cited
US5361373A
Cited
US5493239A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-16 | 2000-12-16 | 2001-06-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-16 | 2004-12-16 | 2005-06-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-16 | 2008-12-16 | 2009-06-17 | $7700.00 | Window Closed / Lapsed |