Method of doping trench sidewalls before trench etching

Claim 1

A method of suppressing formation of a parasitic edge transistor at upper edges of an isolation structure formed in a region of a substrate of an integrated circuit, said method comprising the sequential steps of: depositing a first insulating layer on a semiconductor substrate; forming at least one opening having sidewalls separated by a width in said first insulating layer; depositing a second insulating layer of a conformal material on said first insulating layer and in said opening; anisotropically etching said second insulating layer to form spacers on the sidewalls of said opening and a reduced opening of a lesser width in the first insulating layer; implanting impurities of the same type as the semiconductor substrate but of higher concentration in the semiconductor substrate through said reduced opening and then annealing to laterally diffuse the impurities under said spacers; removing a vertical portion of the semiconductor substrate aligned with said reduced opening to form a trench in said substrate of a width of essentially the same width as said lessor width; and filling said trench with a material to form an isolation structure with high concentration impurity regions abutting the upper edges of the trench at and near the surface of the semiconductor substrate.

Claim 2

A method of suppressing formation of a parasitic edge transistor at upper edges of an isolation structure formed in a region of a substrate of an integrated circuit, said method comprising the sequential steps of: depositing a first insulating layer on a semiconductor substrate; forming at least one opening having sidewalls separated by a width in said first insulating layer; depositing a second insulating layer of a conformal material on said first insulating layer and in said opening; anisotropically etching said second insulating layer to form spacers on the sidewalls of said opening and a reduced opening of a lesser width in the first insulating layer; implanting impurities of the same type as the semiconductor substrate but of higher concentration in the semiconductor substrate through said reduced opening and then annealing to laterally diffuse the impurities under said spacers; removing a vertical portion of the semiconductor substrate aligned with said reduced opening to form a trench in said substrate of a width of essentially the same width as said lessor width; and filling said trench with a material to form an isolation structure with high concentration impurity regions abutting the upper edges of the trench at and near the surface of the semiconductor substrate.

Claim 12

A method of suppressing formation of a parasitic edge transistor at upper edges of isolation structures formed in regions of a substrate of an integrated circuit, said method comprising the sequential steps of: depositing a first insulating layer on a semiconductor substrate; forming a plurality of openings, each having sidewalls separated by a width in said first insulating layer; depositing a second insulating layer of a conformal material on said first insulating layer and in said openings; anisotropically etching said second insulating layer to form spacers on each of the sidewalls of said openings and reduced openings of a lesser width in the first insulating layer; implanting impurities of the same type as the semiconductor substrate but of higher concentration in the semiconductor substrate through said reduced openings and then annealing to laterally diffuse the impurities under said spacers; removing a vertical portion of the semiconductor substrate aligned with said reduced openings to form trenches in said substrate, each of a width of essentially the same width as said lessor width; and filling said trench with a material to form isolation structures each with high concentration impurity regions abutting the upper edges of the trenches at and near the surface of the semiconductor substrate.

Claim 13

A method of suppressing formation of a parasitic edge transistor at upper edges of isolation structures formed in regions of a substrate of an integrated circuit, said method comprising the sequential steps of: depositing a first insulating layer on a semiconductor substrate; forming a plurality of openings, each having sidewalls separated by a width in said first insulating layer; depositing a second insulating layer of a conformal material on said first insulating layer and in said openings; anisotropically etching said second insulating layer to form spacers on each of the sidewalls of said openings and reduced openings of a lesser width in the first insulating layer; implanting impurities of the same type as the semiconductor substrate but of higher concentration in the semiconductor substrate through said reduced openings and then annealing to laterally diffuse the impurities under said spacers; removing a vertical portion of the semiconductor substrate aligned with said reduced openings to form trenches in said substrate, each of a width of essentially the same width as said lessor width; and filling said trench with a material to form isolation structures each with high concentration impurity regions abutting the upper edges of the trenches at and near the surface of the semiconductor substrate.