Bit-refreshable method and circuit for refreshing a nonvolatile flash memory

Claim 5

The method of claim 2, further comprising the steps of: after all of the incrementing step counts have been generated: generating a charge inhibit signal associated with the memory cell; generating a step count pattern which has decrementing step counts; applying stepwise increasing program verify signals based on the decrementing step counts to the memory array for reading the memory cell; comparing the data with a complement of the decrementing step counts, and resetting the charge inhibit signal to a charge enable signal when the data is greater than or equal to the complement of the decrementing step counts; resetting the charge enable signal back to the charge inhibit signal when the memory cell does not conduct after applying the program verify signals corresponding to the decrementing step counts to the memory array; and if the charge enable signal is present after applying one of the program verify signals to the memory array, charging the memory cell so that the threshold voltage thereof becomes higher than said one of the program verify signals to cure the memory cell of undesired charge loss.

Claim 10

The method of claim 5, wherein, in step (c6), the scanning mode register is toggled and the scanning mode bit in the second portion of the attribute memory is rewritten to a flipped state when the data matches the scanning mode bit and the scanned address is the final address of the attribute memory.

Claim 11

A refreshing circuit for refreshing a flash memory with a multi-level memory array, comprising: a read-write controller including: a read/write circuit having: a master latch for latching data corresponding to that stored in a memory cell of the memory array; and a slave latch for generating a discharge enable signal associated with the memory cell; and a step counter for generating a step count pattern which has incrementing step counts; a voltage generator coupled to said step counter and the memory array, said voltage generator applying stepwise decreasing erase verify signals based on the incrementing step counts from said step counter to the memory array for reading the memory cell; said read/write circuit further having: a level comparator coupled to said master latch, said step counter and said slave latch, said level comparator comparing the data with a complement of the incrementing step counts, and resetting the discharge enable signal to a discharge inhibit signal when the data is greater than or equal to the complement of the incrementing step counts; and a sense amplifier coupled to the memory array and said slave latch, said sense amplifier sensing conduction of the memory cell after said voltage generator applies the erase verify signals corresponding to the incrementing step counts to the memory array and resetting the discharge enable signal to the discharge inhibit signal when the memory cell conducts; said read/write controller further including a detecting circuit coupled to said slave latch for detecting presence of the discharge enable signal; and a control circuit coupled to said master latch, said detecting circuit and said voltage generator, said control circuit controlling latching of the data by said master latch upon initiation of a refresh operation, said control circuit being controlled by said detecting circuit to control in turn said voltage generator to permit discharging of the memory cell so that a threshold voltage thereof becomes lower than one of the erase verify signals to cure the memory cell of undesired charge gain upon detection by said detecting circuit that the discharge enable signal is still present after application of said one of the erase verify signals.

Claim 12

A refreshing circuit for refreshing a flash memory with a multi-level memory array, comprising: a read-write controller including: a read/write circuit having: a master latch for latching data corresponding to that stored in a memory cell of the memory array; and a slave latch for generating a discharge enable signal associated with the memory cell; and a step counter for generating a step count pattern which has incrementing step counts; a voltage generator coupled to said step counter and the memory array, said voltage generator applying stepwise decreasing erase verify signals based on the incrementing step counts from said step counter to the memory array for reading the memory cell; said read/write circuit further having: a level comparator coupled to said master latch, said step counter and said slave latch, said level comparator comparing the data with a complement of the incrementing step counts, and resetting the discharge enable signal to a discharge inhibit signal when the data is greater than or equal to the complement of the incrementing step counts; and a sense amplifier coupled to the memory array and said slave latch, said sense amplifier sensing conduction of the memory cell after said voltage generator applies the erase verify signals corresponding to the incrementing step counts to the memory array and resetting the discharge enable signal to the discharge inhibit signal when the memory cell conducts; said read/write controller further including a detecting circuit coupled to said slave latch for detecting presence of the discharge enable signal; and a control circuit coupled to said master latch, said detecting circuit and said voltage generator, said control circuit controlling latching of the data by said master latch upon initiation of a refresh operation, said control circuit being controlled by said detecting circuit to control in turn said voltage generator to permit discharging of the memory cell so that a threshold voltage thereof becomes lower than one of the erase verify signals to cure the memory cell of undesired charge gain upon detection by said detecting circuit that the discharge enable signal is still present after application of said one of the erase verify signals.

Claim 13

The refreshing circuit of claim 7, wherein: said slave latch further generates a charge inhibit signal associated with the memory cell; said step counter further generating a step count pattern which has a plurality of decrementing step counts after generating all of the incrementing step counts; said voltage generator further applying stepwise increasing program verify signals based on the decrementing step counts to the memory array for reading the memory cell; said level comparator further comparing the data with a complement of the decrementing step counts and resetting the charge inhibit signal to a charge enable signal when the data is greater than or equal to the complement of the decrementing step counts; said sense amplifier further resetting the charge enable signal back to the charge inhibit signal when the memory cell does not conduct after said voltage generator applies the program verify signals corresponding to the decrementing step counts to the memory array; and said detecting circuit further detecting presence of the charge enable signal after said voltage generator applies one of the program verify signals and controlling said control circuit to control, in turn, said voltage generator to permit charging of the memory cell so that the threshold voltage thereof becomes higher than said one of the program verify signals to cure the memory cell of undesired charge loss.

Claim 14

The refreshing circuit of claim 7, wherein said control circuit is adapted to receive a command set from an off-chip controller to initiate the refresh operation.

Claim 15

The refreshing circuit of claim 7, further comprising a sequencer coupled to and controlled by said control circuit so as to generate address data internally for accessing the memory cells of the memory array sequentially during the refresh operation.

Claim 16

The refreshing circuit of claim 7, further comprising automatic means coupled to said control circuit for initiating the refresh operation, said automatic means comprising: a non-volatile attribute memory coupled to said control circuit and having a first memory portion for storing a starting address, a second memory portion for storing a scanning mode bit, and a third memory portion for storing a write cycle record; an address register coupled to said control circuit and said attribute memory, said control circuit loading the starting address into said address register during every power-on period; a scanning mode register coupled to said control circuit and said attribute memory, said control circuit loading the starting mode bit into said scanning mode register during every power-on period; and a scanning counter coupled to said address register and said control circuit; said control circuit loading the starting address from said address register into said scanning counter so as to scan said third memory portion of said attribute memory at an address corresponding to an address output of said scanning counter after each write cycle of the flash memory, said control circuit comparing data at scanned address of said attribute memory with the scanning mode bit; if the data matches the scanning mode bit, and the scanned address is not a final address of said attribute memory, said control circuit controlling said scanning counter to increment the address output thereof for scanning another address of said attribute memory and for comparing data at said another address with the scanning mode bit; if the data does not match the scanning mode bit, said control circuit writing at the scanned address such that the data thereat matches the scanning mode bit, and stopping the scanning of said attribute memory; and if the data matches the scanning mode bit, and the scanned address is a final address of said attribute memory, said control circuit initiating the refresh operation for refreshing the memory array.

Claim 17

The refreshing circuit of claim 11, wherein said control circuit toggles said scanning mode register and rewrites the scanning mode bit in said second portion of said attribute memory to a flipped state when the data matches the scanning mode bit and the scanned address is the final address of said attribute memory.

Claim 18

A refreshing circuit for refreshing a flash memory with a multi-level memory array, comprising: a read-write controller including: a read/write circuit having: a master latch for latching data corresponding to that stored in a memory cell of the memory array; and a slave latch for generating a charge inhibit signal associated with the memory cell; and a step counter for generating a step count pattern which has decrementing step counts; a voltage generator coupled to said step counter and the memory array, said voltage generator applying stepwise increasing program verify signals based on the decrementing step counts from said step counter to the memory array for reading the memory cell; said read/write circuit further having: a level comparator coupled to said master latch, said step counter and said slave latch, said level comparator comparing the data with a complement of the decrementing step counts and resetting the charge inhibit signal to a charge enable signal when the data is greater than or equal to the complement of the decrementing step counts; and a sense amplifier coupled to the memory array and said slave latch, said sense amplifier sensing conduction of the memory cell after said voltage generator applies the program verify signals corresponding to the decrementing step counts to the memory array and resetting the charge enable signal back to the charge inhibit signal when the memory cell does not conduct; said read/write controller further including a detecting circuit coupled to said slave latch for detecting presence of the charge enable signal; and a control circuit coupled to said master latch, said detecting circuit and said voltage generator, said control circuit controlling latching of the data by said master latch upon initiation of a refresh operation, said control circuit being controlled by said detecting circuit to control in turn said voltage generator to permit charging of the memory cell so that a threshold voltage thereof becomes higher than one of the program verify signals to cure the memory cell of undesired charge loss upon detection by said detecting circuit that the charge enable signal is still present after application of said one of the program verify signals.

Claim 19

A refreshing circuit for refreshing a flash memory with a multi-level memory array, comprising: a read-write controller including: a read/write circuit having: a master latch for latching data corresponding to that stored in a memory cell of the memory array; and a slave latch for generating a charge inhibit signal associated with the memory cell; and a step counter for generating a step count pattern which has decrementing step counts; a voltage generator coupled to said step counter and the memory array, said voltage generator applying stepwise increasing program verify signals based on the decrementing step counts from said step counter to the memory array for reading the memory cell; said read/write circuit further having: a level comparator coupled to said master latch, said step counter and said slave latch, said level comparator comparing the data with a complement of the decrementing step counts and resetting the charge inhibit signal to a charge enable signal when the data is greater than or equal to the complement of the decrementing step counts; and a sense amplifier coupled to the memory array and said slave latch, said sense amplifier sensing conduction of the memory cell after said voltage generator applies the program verify signals corresponding to the decrementing step counts to the memory array and resetting the charge enable signal back to the charge inhibit signal when the memory cell does not conduct; said read/write controller further including a detecting circuit coupled to said slave latch for detecting presence of the charge enable signal; and a control circuit coupled to said master latch, said detecting circuit and said voltage generator, said control circuit controlling latching of the data by said master latch upon initiation of a refresh operation, said control circuit being controlled by said detecting circuit to control in turn said voltage generator to permit charging of the memory cell so that a threshold voltage thereof becomes higher than one of the program verify signals to cure the memory cell of undesired charge loss upon detection by said detecting circuit that the charge enable signal is still present after application of said one of the program verify signals.

Claim 20

The refreshing circuit of claim 13, wherein said control circuit is adapted to receive a command set from an off-chip controller to initiate the refresh operation.

Claim 21

The refreshing circuit of claim 13, further comprising a sequencer coupled to and controlled by said control circuit so as to generate address data internally for accessing the memory cells of the memory array sequentially during the refresh operation.

Claim 22

The refreshing circuit of claim 13, further comprising automatic means coupled to said control circuit for initiating the refresh operation, said automatic means comprising: a non-volatile attribute memory coupled to said control circuit and having a first memory portion for storing a starting address, a second memory portion for storing a scanning mode bit, and a third memory portion for storing a write cycle record; an address register coupled to said control circuit and said attribute memory, said control circuit loading the starting address into said address register during every power-on period; a scanning mode register coupled to said control circuit and said attribute memory, said control circuit loading the starting mode bit into said scanning mode register during every power-on period; and a scanning counter coupled to said address register and said control circuit; said control circuit loading the starting address from said address register into said scanning counter so as to scan said third memory portion of said attribute memory at an address corresponding to an address output of said scanning counter after each write cycle of the flash memory, said control circuit comparing data at scanned address of said attribute memory with the scanning mode bit; if the data matches the scanning mode bit, and the scanned address is not a final address of said attribute memory, said control circuit controlling said scanning counter to increment the address output thereof for scanning another address of said attribute memory and for comparing data at said another address with the scanning mode bit; if the data does not match the scanning mode bit, said control circuit writing at the scanned address such that the data thereat matches the scanning mode bit, and stopping the scanning of said attribute memory; and if the data matches the scanning mode bit, and the scanned address is a final address of said attribute memory, said control circuit initiating the refresh operation for refreshing the memory array.

Claim 23

The refreshing circuit of claim 16, wherein said control circuit toggles said scanning mode register and rewrites the scanning mode bit in said second portion of said attribute memory to a flipped state when the data matches the scanning mode bit and the scanned address is the final address of said attribute memory.

Claim 24

An automatic circuit for initiating a refresh operation in a flash memory with a memory array and a refreshing circuit, said automatic circuit comprising: a non-volatile attribute memory coupled to the refreshing circuit and having a first memory portion for storing a starting address, a second memory portion for storing a scanning mode bit, and a third memory portion for storing a write cycle record; an address register coupled to the refreshing circuit and said attribute memory, the refreshing circuit loading the starting address into said address register during every power-on period; a scanning mode register coupled to the refreshing circuit and said attribute memory, the refreshing circuit loading the starting mode bit into said scanning mode register during every power-on period; and a scanning counter coupled to said address register and the refreshing circuit; the refreshing circuit loading the starting address from said address register into said scanning counter so as to scan said third memory portion of said attribute memory at an address corresponding to an address output of said scanning counter after each write cycle of the flash memory, the refreshing circuit comparing data at scanned address of said attribute memory with the scanning mode bit; if the data matches the scanning mode bit, and the scanned address is not a final address of said attribute memory, the refreshing circuit controlling said scanning counter to increment the address output thereof for scanning another address of said attribute memory and for comparing data at said another address with the scanning mode bit; if the data does not match the scanning mode bit, the refreshing circuit writing at the scanned address such that the data thereat matches the scanning mode bit, and stopping the scanning of said attribute memory; and if the data matches the scanning mode bit, and the scanned address is a final address of said attribute memory, the refreshing circuit initiating the refresh operation for refreshing the memory array.

Claim 25

An automatic circuit for initiating a refresh operation in a flash memory with a memory array and a refreshing circuit, said automatic circuit comprising: a non-volatile attribute memory coupled to the refreshing circuit and having a first memory portion for storing a starting address, a second memory portion for storing a scanning mode bit, and a third memory portion for storing a write cycle record; an address register coupled to the refreshing circuit and said attribute memory, the refreshing circuit loading the starting address into said address register during every power-on period; a scanning mode register coupled to the refreshing circuit and said attribute memory, the refreshing circuit loading the starting mode bit into said scanning mode register during every power-on period; and a scanning counter coupled to said address register and the refreshing circuit; the refreshing circuit loading the starting address from said address register into said scanning counter so as to scan said third memory portion of said attribute memory at an address corresponding to an address output of said scanning counter after each write cycle of the flash memory, the refreshing circuit comparing data at scanned address of said attribute memory with the scanning mode bit; if the data matches the scanning mode bit, and the scanned address is not a final address of said attribute memory, the refreshing circuit controlling said scanning counter to increment the address output thereof for scanning another address of said attribute memory and for comparing data at said another address with the scanning mode bit; if the data does not match the scanning mode bit, the refreshing circuit writing at the scanned address such that the data thereat matches the scanning mode bit, and stopping the scanning of said attribute memory; and if the data matches the scanning mode bit, and the scanned address is a final address of said attribute memory, the refreshing circuit initiating the refresh operation for refreshing the memory array.

Claim 26

The automatic circuit of claim 18, wherein the refreshing circuit toggles said scanning mode register and rewrites the scanning mode bit in said second portion of said attribute memory to a flipped state when the data matches the scanning mode bit and the scanned address is the final address of said attribute memory.