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US5767701A
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Synchronous contention prevention logic for bi-directional signals
Assignee: Cypress Semiconductor Corp
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Filing: 1996-06-28
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Granted: 1998-06-16
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Expires: 2016-06-28
Abstract
Abstract A synchronous contention prevention circuit for a bi-directional bus. The synchronous contention prevention circuit comprises a synchronous anticontention circuit coupled to a first input/output circuit. The synchronous anticontention circuit receives a driver select signal and a clock signal. The first input/output circuit has a first input coupled to the synchronous anticontention circuit and a first output. When the driver select signal is in a first logic state, the first input/output circuit is disabled from driving the first output. Subsequently, the driver select signal transitions from the first logic state to a second logic state. After the driver select signal transition to the second logic state, the synchronous anticontention circuit generates a first signal in response to a first transition of the clock signal. The synchronous anticontention circuit then generates a second signal in response to the first signal and a second transition of the clock signal. The second signal enables the first input/output circuit to drive the first output. The first output may be coupled to a bi-directional bus.
Inventors
- 👤 Garrett Choy
- 👤 W. Alfred Graf, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:39
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
129 words
A synchronous contention prevention circuit comprising: a synchronous anticontention circuit receiving a driver select signal and a clock signal; and a first input/output circuit having a first input coupled to the synchronous anticontention circuit and a first output, wherein: when the driver select signal is in a first logic state, the first input/output circuit is disabled from driving the first output; when the driver select signal transitions from the first logic state to a second logic state, the synchronous anticontention circuit generates: (a) a first signal in response to a first transition of the clock signal; and (b) a second signal in response to the first signal and a second transition of the clock signal, wherein the second signal enables the first input/output circuit to drive the first output.
Claim 2
Dependent Claim
129 words
A synchronous contention prevention circuit comprising: a synchronous anticontention circuit receiving a driver select signal and a clock signal; and a first input/output circuit having a first input coupled to the synchronous anticontention circuit and a first output, wherein: when the driver select signal is in a first logic state, the first input/output circuit is disabled from driving the first output; when the driver select signal transitions from the first logic state to a second logic state, the synchronous anticontention circuit generates: (a) a first signal in response to a first transition of the clock signal; and (b) a second signal in response to the first signal and a second transition of the clock signal, wherein the second signal enables the first input/output circuit to drive the first output.
Claim 3
Dependent Claim
19 words
The synchronous contention prevention circuit of claim 1, wherein the first output is for coupling to a bi-directional bus.
Claim 4
Dependent Claim
120 words
The synchronous contention prevention circuit of claim 1, wherein the synchronous anticontention circuit comprises: an anticontention circuit having an input receiving the driver select signal; and a synchronous delay circuit coupled to the anticontention circuit and receiving the clock signal, wherein: when the driver select signal transitions from the first logic state to the second logic state, the anticontention circuit generates the first signal and the synchronous delay circuit outputs the first signal in response to the first transition of the clock signal; in response to the first signal, the anticontention circuit generates the second signal; and in response to the second transition of the clock signal, the synchronous delay circuit outputs the second signal to the first input/output circuit.
Claim 5
Dependent Claim
66 words
The synchronous contention prevention circuit of claim 3, wherein the anticontention circuit comprises: a first logic element receiving the driver select signal and the first signal, the first logic element having an output coupled to the synchronous delay circuit; and a second logic element receiving the driver select signal and the second signal, the second logic element having an output coupled to the synchronous delay circuit.
Claim 6
Dependent Claim
67 words
The synchronous contention prevention circuit of claim 3, wherein the synchronous delay circuit comprises: a first register receiving the first signal from the anticontention circuit and outputting the first signal in response to the first transition of the clock signal; and a second register receiving the second signal from the anticontention circuit and outputting the second signal in response to the second transition of the clock signal.
Claim 7
Dependent Claim
31 words
The synchronous contention prevention circuit of claim 1, further comprising a driver select control circuit coupled to the synchronous anticontention circuit, the driver select control circuit generating the driver select signal.
Claim 8
Dependent Claim
79 words
The synchronous contention prevention circuit of claim 1, further comprising a second input/output circuit having a second input coupled to the synchronous anticontention circuit and a second output, wherein: when the driver select signal is in the first logic state, the second input/output circuit drives the second output; and when the synchronous anticontention circuit generates the first signal in response to the first transition of the clock signal the second input/output circuit is disabled from driving the second output.
Claim 9
Dependent Claim
94 words
The synchronous contention prevention circuit of claim 7, further comprising a bi-directional bus coupled to the first output of the first input/output circuit and the second output of the second input/output circuit, wherein: when the driver select signal is in the first logic state: (a) the second output of the second input/output circuit drives the bi-directional bus; and (b) the first output of the first input/output circuit is disabled from driving the bi-directional bus; when synchronous anticontention circuit generates the second signal, the first output of the first input/output circuit drives the bi-directional bus.
Claim 10
Dependent Claim
32 words
The synchronous contention prevention circuit of claim 1, further comprising a feedback circuit coupled to the first signal, wherein the feedback circuit couples the first signal back to the synchronous anticontention circuit.
Claim 11
Dependent Claim
15 words
The synchronous contention prevention circuit of claim 9, wherein the feedback circuit comprises a buffer.
Claim 12
Dependent Claim
92 words
The synchronous contention prevention circuit of claim 10, wherein the buffer comprises: an SR register having an S input, an R input, and an output, wherein the S input and the output of the SR register are coupled to the first signal and synchronous anticontention circuit, respectively; and an inverter having an input and an output, wherein the input of the inverter is coupled to the S input of the SR register and the first signal, and the output of the inverter is coupled to the R input of the SR register.
Claim 13
Dependent Claim
54 words
The synchronous contention prevention circuit of claim 10, wherein the feedback circuit further comprises a logic element having a first input, a second input, and an output, the first input receiving the first signal, the second input coupled to the buffer, and the output of the logic element coupled to the synchronous anticontention circuit.
Claim 14
Dependent Claim
23 words
The synchronous contention prevention circuit of claim 12, wherein the logic element comprises an AND gate, an OR gate, or any combination thereof.
Claim 15
Dependent Claim
143 words
A system comprising: a first device including the synchronous contention prevention circuit of claim 1; a second device comprising a second input/output circuit having a second input coupled to the synchronous anticontention circuit and a second output; and a bi-directional bus coupled to the first output of the first input/output circuit and the second output of the second input/output circuit, wherein: when the driver select signal is in the first logic state: (a) the second output of the second input/output circuit drives the bi-directional bus; and (b) the first output of the first input/output circuit is disabled from driving the bi-directional bus; when the synchronous anticontention circuit generates the first signal, the second output is disabled from driving the bi-directional bus; and when the synchronous anticontention circuit generates the second signal, the first output of the first input/output circuit drives the bi-directional bus.
Claim 16
Dependent Claim
27 words
The system of claim 14, further comprising a driver select circuit coupled to the synchronous anticontention circuit, wherein the driver select circuit generates the driver select signal.
Claim 17
Dependent Claim
30 words
The system of claim 14, wherein the second device further comprises a feedback circuit having an input receiving the first signal and an output coupled to the synchronous anticontention circuit.
Claim 18
Dependent Claim
111 words
A synchronous contention prevention circuit comprising: means for receiving a driver select signal and a clock signal; means for generating a first signal in response to a transition of the driver select signal and a first transition of the clock signal; means for generating a second signal in response to the first signal and a second transition of the clock signal; and first input/output means having a first input and a first output, the first input/output means for disabling driving of the first output when the driver select signal is in a first logic state, and the first input/output means for driving the first output in response to the second signal.
Claim 19
Dependent Claim
111 words
A synchronous contention prevention circuit comprising: means for receiving a driver select signal and a clock signal; means for generating a first signal in response to a transition of the driver select signal and a first transition of the clock signal; means for generating a second signal in response to the first signal and a second transition of the clock signal; and first input/output means having a first input and a first output, the first input/output means for disabling driving of the first output when the driver select signal is in a first logic state, and the first input/output means for driving the first output in response to the second signal.
Claim 20
Dependent Claim
59 words
The synchronous contention prevention circuit of claim 17, further comprising second input/output means having a second input and a second output, the second input/output means for driving the second output when the driver select signal is in the first logic state, and the second input/output means for disabling driving of the second output in response to the first signal.
Claim 21
Independent Claim
91 words
A method of synchronously preventing contention on a bi-directional bus, the method comprising the steps of: disabling a first input/output circuit from driving a bi-directional bus in response to a first signal and a first transition of a clock signal, wherein the first signal is generated in response to a first driver select signal; and enabling a second input/output circuit to drive the bi-directional bus in response to a second signal and a second transition of the clock signal, wherein the second signal is generated in response to the first signal.
Claim 22
Independent Claim
91 words
A method of synchronously preventing contention on a bi-directional bus, the method comprising the steps of: disabling a first input/output circuit from driving a bi-directional bus in response to a first signal and a first transition of a clock signal, wherein the first signal is generated in response to a first driver select signal; and enabling a second input/output circuit to drive the bi-directional bus in response to a second signal and a second transition of the clock signal, wherein the second signal is generated in response to the first signal.
Claim 23
Dependent Claim
57 words
The method of claim 19, further comprising the steps of: disabling the second input/output circuit from driving the bi-directional bus in response to a second driver select signal and a third transition of the clock signal; and enabling the first input/output circuit to drive the bi-directional bus in response to a fourth transition of the clock signal.
Claim 24
Dependent Claim
46 words
The method of claim 20, wherein the disabling step further comprises the steps of: generating a first signal in response to the second driver select signal; and disabling the second input/output circuit in response to the first signal and the third transition of the clock signal.
Claim 25
Dependent Claim
44 words
The method of claim 21, wherein the enabling step further comprises the steps of: generating a second signal in response to the first signal; and enabling the first input/output circuit in response to the second signal and the fourth transition of the clock signal.
Claim 26
Dependent Claim
140 words
An electrical device comprising: an input/output circuit; a bi-directional port coupled to the input/output circuit, the bi-directional port being capable of coupling to a bi-directional bus; an input port coupled to the input/output circuit, the input port being capable of receiving a signal from a synchronous anticontention circuit, wherein the signal has: (a) a first logic state enabling the input/output circuit to output data through the bi-directional port; and (b) a second logic state enabling the input/output circuit to receive input data through the bi-directional port; a feedback circuit having an input coupled to the input port and an output; and an output port coupled to the output of the feedback circuit, wherein the feedback circuit is capable of receiving the signal from the input port and causing the output port to output the signal to the synchronous anticontention circuit.
Claim 27
Dependent Claim
140 words
An electrical device comprising: an input/output circuit; a bi-directional port coupled to the input/output circuit, the bi-directional port being capable of coupling to a bi-directional bus; an input port coupled to the input/output circuit, the input port being capable of receiving a signal from a synchronous anticontention circuit, wherein the signal has: (a) a first logic state enabling the input/output circuit to output data through the bi-directional port; and (b) a second logic state enabling the input/output circuit to receive input data through the bi-directional port; a feedback circuit having an input coupled to the input port and an output; and an output port coupled to the output of the feedback circuit, wherein the feedback circuit is capable of receiving the signal from the input port and causing the output port to output the signal to the synchronous anticontention circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-15 | 2001-12-15 | 2002-06-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-15 | 2005-12-15 | 2006-06-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-15 | 2009-12-15 | 2010-06-16 | $7700.00 | Window Closed / Lapsed |