US5761483A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Optimizing and operating a time multiplexed programmable logic device
Assignee: Xilinx Inc
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Filing: 1995-08-18
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Granted: 1998-06-02
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Expires: 2015-08-18
Abstract
Abstract A method of optimizing a time multiplexed programmable logic device (PLD) includes entering a circuit design for the PLD, mapping the design to the physical resources of the PLD (wherein the physical resources include configurable logic elements), determining an appropriate micro cycle for each configurable logic element in the design, placing the resources on the PLD, and connecting the resources. Optimizing the design may include reducing the number of look up tables or reducing the logic depth of the look up tables. If the configurable logic elements include sequential logic elements, then the optimizing step includes rescheduling the sequential logic elements. A method of operating a time multiplexed PLD in a logic engine mode includes programming the PLD to implement a design in stages, wherein each stage is one configuration, sequencing the PLD through all the configurations, and storing the results of the logic performed in one configuration in a plurality of micro registers for use in subsequent configurations. In one embodiment, the PLD includes a plurality of combinational elements and sequential logic elements, wherein the values stored by the sequential logic elements are stored in the micro registers.
Inventors
- 👤 Stephen M. Trimberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:01
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17758; G; G06; G06F; G06F30/00; G06F30/30; G06F30/34; H03K19/17704; H03K19/1776
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
67 words
A computer-implemented method of designing a time multiplexed programmable logic device, comprising: entering a circuit design for said programmable logic device; mapping said circuit design to the physical resources of said programmable logic device, wherein said physical resources include configurable logic elements; determining an appropriate micro cycle for each configurable logic element in said design; placing said resources on said programmable logic device; and connecting said resources.
Claim 2
Dependent Claim
67 words
A computer-implemented method of designing a time multiplexed programmable logic device, comprising: entering a circuit design for said programmable logic device; mapping said circuit design to the physical resources of said programmable logic device, wherein said physical resources include configurable logic elements; determining an appropriate micro cycle for each configurable logic element in said design; placing said resources on said programmable logic device; and connecting said resources.
Claim 3
Dependent Claim
11 words
The computer-implemented method of claim 1 further comprising optimizing said design.
Claim 4
Dependent Claim
22 words
The computer-implemented method of claim 2 wherein said optimizing includes reducing the number of said configurable logic elements to implement said design.
Claim 5
Dependent Claim
23 words
The computer-implemented method of claim 2 wherein said optimizing includes reducing the logic depth of said configurable logic elements to implement said design.
Claim 6
Dependent Claim
23 words
The computer-implemented method of claim 2 wherein said circuit design includes sequential logic elements and said optimizing includes rescheduling said sequential logic elements.
Claim 7
Dependent Claim
68 words
A computer-implemented method of designing a time multiplexed programmable logic device, comprising: entering a circuit design for said programmable logic device; mapping said design to the physical resources of said programmable logic device, wherein said physical resources include configurable logic elements; simultaneously determining an appropriate micro cycle for each configurable logic element in said design and placing said resources on said programmable logic device; and connecting said resources.
Claim 8
Dependent Claim
68 words
A computer-implemented method of designing a time multiplexed programmable logic device, comprising: entering a circuit design for said programmable logic device; mapping said design to the physical resources of said programmable logic device, wherein said physical resources include configurable logic elements; simultaneously determining an appropriate micro cycle for each configurable logic element in said design and placing said resources on said programmable logic device; and connecting said resources.
Claim 9
Independent Claim
47 words
A method of time multiplexing a programmable logic device comprising: scheduling the logic of said programmable logic device to be evaluated in a plurality of micro cycles; and scheduling the logic of a critical path in said programmable logic device to be evaluated in sequential micro cycles.
Claim 10
Independent Claim
47 words
A method of time multiplexing a programmable logic device comprising: scheduling the logic of said programmable logic device to be evaluated in a plurality of micro cycles; and scheduling the logic of a critical path in said programmable logic device to be evaluated in sequential micro cycles.
Claim 11
Dependent Claim
67 words
A computer-implemented method of operating a time multiplexed programmable logic device in a logic engine mode, comprising: programming said programmable logic device to implement a design in stages, wherein each stage is one configuration; sequencing said programmable logic device through at least one of the configurations; storing the results of the logic performed in one configuration in a plurality of micro registers for use in subsequent configurations.
Claim 12
Dependent Claim
67 words
A computer-implemented method of operating a time multiplexed programmable logic device in a logic engine mode, comprising: programming said programmable logic device to implement a design in stages, wherein each stage is one configuration; sequencing said programmable logic device through at least one of the configurations; storing the results of the logic performed in one configuration in a plurality of micro registers for use in subsequent configurations.
Claim 13
Dependent Claim
36 words
The computer-implemented method of claim 8 wherein said programmable logic device includes a plurality of combinational elements and sequential logic elements, wherein the values stored by said sequential logic elements are stored in said micro registers.
Claim 14
Dependent Claim
28 words
The computer-implemented method of claim 8 further including isolating the bits associated with an active configuration during an operation on the bits of at least one inactive configuration.
Claim 15
Dependent Claim
19 words
The computer-implemented method of claim 10 wherein said bits of at least one inactive configuration are user data bits.
Claim 16
Dependent Claim
33 words
The computer-implemented method of claim 11 further including a plurality of memory slices on said programmable logic device, wherein the bits associated with said active configuration are provided in at least two slices.
References Cited (Backward Citations)
US3775756A
Cited
US4237545A
Cited
JPS53121537A
Cited
US4288658A
Cited
US4434461A
Cited
US4750155A
Cited
US4821233A
Cited
US5019996A
Cited
US5426744A
Cited
US5144242A
Cited
US5469577A
Cited
US5224056A
Cited
US5426738A
Cited
US5513124A
Cited
US5377331A
Cited
US5521835A
Cited
US5432388A
Cited
US5349248A
Cited
US5530654A
Cited
US5426378A
Cited
US5526276A
Cited
US5583450A
Cited
US5600263A
Cited
US5629637A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-01 | 2001-12-01 | 2002-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-01 | 2005-12-01 | 2006-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-01 | 2009-12-01 | 2010-06-02 | $7700.00 | Window Closed / Lapsed |