Interoperability with multiple instruction sets

Claim 1

Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a program counter register for indicating the address of a next program instruction word in data memory storing instruction words to be executed; program counter register modifier, for modifying the contents of said program counter register in response to a current program instruction word; a controller, responsive to one or more predetermined indicator bits of said program counter register, for controlling said processor core to execute program instruction words of a current instruction set selected from said predetermined plurality of instruction sets and specified by the state of said one or more indicator bits of said program counter register, the one or more indicator bits of the program counter register being one or more least significant bits of the program counter register; a first instruction decoder for decoding program instruction words of a first instruction set; and a second instruction decoder for decoding program instruction words of a second instruction set; in which said controller is operable to control either said first instruction decoder or said second instruction decoder to decode a current program instruction word; and in which program instruction words of said first instruction set are X-bit program instruction words, and program instruction words of said second instruction set are Y-bit program instruction words, Y being different to X.