Patent US5757819A successfully refreshed from Google Patents.
US5757819A
Expired / Lapsed
US
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Integrated circuit test controller
Assignee: ARM Ltd
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Filing: 1996-12-03
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Granted: 1998-05-26
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Expires: 2016-12-03
Abstract
Abstract An integrated circuit 2 implementing JTAG debugging and analysis functions has an IDCODE Instruction which returns predetermined data characteristic of the integrated circuit, e.g. manufacturer, part number and version. A portion 20 of the serial test scan chain of the integrated circuit 2 is reused to load and then serially output this identifying data. The serial input of the test and debugging system is connected during such IDCODE Instructions to the start of the portion 20 of the serial test scan chain. This enables the identifying data of a plurality of integrated circuits with linked serial test scan chains to successively output their identifying data in one operation.
Inventors
- 👤 Simon Anthony Segars
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:16
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558; G01R31/318561; G01R31/31702; G06; G06F; G06F11/00; G06F11/006
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
249 words
An integrated circuit comprising: (i) a circuit unit for performing an operational function within said integrated circuit; (ii) a serial test scan chain formed of a plurality of scan chain cells including a first portion consisting of thirty-two scan chain cells and a second portion including additional scan chain cells, said serial test scan chain being coupled to said circuit unit for capturing signals from and applying signals to predetermined points within said circuit unit; and (iii) a scan chain controller for controlling test operation of said serial test scan chain and having a serial data input for input of serial data from outside of said integrated circuit and a serial data output for output of serial data to outside of said integrated circuit; (iv) wherein said scan chain controller is responsive to an identifying-data-requesting-instruction input via said serial data input to control loading of predetermined identifying data characteristic of and stored within said integrated circuit into said first portion of said serial test scan chain and to control serial output via said serial data output of said identifying data from said first portion of said serial test scan chain; and further comprising; (v) a scan chain multiplexer disposed within said serial test scan chain and responsive to said identifying-data-requesting-instruction to connect said first portion of said serial test scan chain between said serial data input and said serial data output and to bypass said second portion including said additional scan chain cells of said serial test scan chain.
Claim 2
Dependent Claim
249 words
An integrated circuit comprising: (i) a circuit unit for performing an operational function within said integrated circuit; (ii) a serial test scan chain formed of a plurality of scan chain cells including a first portion consisting of thirty-two scan chain cells and a second portion including additional scan chain cells, said serial test scan chain being coupled to said circuit unit for capturing signals from and applying signals to predetermined points within said circuit unit; and (iii) a scan chain controller for controlling test operation of said serial test scan chain and having a serial data input for input of serial data from outside of said integrated circuit and a serial data output for output of serial data to outside of said integrated circuit; (iv) wherein said scan chain controller is responsive to an identifying-data-requesting-instruction input via said serial data input to control loading of predetermined identifying data characteristic of and stored within said integrated circuit into said first portion of said serial test scan chain and to control serial output via said serial data output of said identifying data from said first portion of said serial test scan chain; and further comprising; (v) a scan chain multiplexer disposed within said serial test scan chain and responsive to said identifying-data-requesting-instruction to connect said first portion of said serial test scan chain between said serial data input and said serial data output and to bypass said second portion including said additional scan chain cells of said serial test scan chain.
Claim 3
Dependent Claim
33 words
An integrated circuit as claimed in claim 1, wherein said scan chain controller includes a multiplexer for connecting one of a plurality of points within said integrated circuit to said serial data output.
Claim 4
Dependent Claim
44 words
An integrated circuit as claimed in claim 1, wherein said identifying data includes one or more of: data identifying a manufacturer of said integrated circuit; data identifying a part number of said integrated circuit; and data identifying a version number for said integrated circuit.
Claim 5
Dependent Claim
21 words
An integrated circuit as claimed in claim 1, wherein said identifying data is stored within non-volatile storage within said integrated circuit.
Claim 6
Dependent Claim
83 words
An integrated circuit as claimed in claim 1, wherein said scan chain multiplexer comprises an input multiplexer for connecting said first portion of said serial test scan chain into which said identifying data is loaded to one of said serial data input or an output of said second portion of said serial test scan chain immediately preceding said first portion into which said identifying data is loaded, said input multiplexer switching to connect to said serial data input in response to said identifying-data-requesting-instruction.
Claim 7
Independent Claim
235 words
A method of operating an integrated circuit including a serial test scan chain formed of a plurality of scan chain cells including a first portion consisting of thirty-two scan chain cells and a second portion including additional scan chain cells, said method comprising the steps of: (i) performing an operational function with a circuit unit within said integrated circuit; (ii) capturing signals from and applying signals to predetermined points within said circuit unit using said serial test scan chain coupled to said circuit unit for; (iii) controlling test operation of said serial test scan chain with a scan chain controller having a serial data input for input of serial data from outside of said integrated circuit and a serial data output for output of serial data to outside of said integrated circuit; (iv) in response to an identifying-data-requesting-instruction input via said serial data input, loading predetermined identifying data characteristic of and stored within said integrated circuit into said first portion of said serial test scan chain, and serially outputting said identifying data via said serial data output from said first portion of said serial test scan chain; and (v) in response to said identifying-data-requesting-instruction connecting said first portion of said serial test scan chain between said serial data input and said serial data output and bypassing said second portion of the scan chain cells not within said first portion of said serial test scan chain.
Claim 8
Independent Claim
235 words
A method of operating an integrated circuit including a serial test scan chain formed of a plurality of scan chain cells including a first portion consisting of thirty-two scan chain cells and a second portion including additional scan chain cells, said method comprising the steps of: (i) performing an operational function with a circuit unit within said integrated circuit; (ii) capturing signals from and applying signals to predetermined points within said circuit unit using said serial test scan chain coupled to said circuit unit for; (iii) controlling test operation of said serial test scan chain with a scan chain controller having a serial data input for input of serial data from outside of said integrated circuit and a serial data output for output of serial data to outside of said integrated circuit; (iv) in response to an identifying-data-requesting-instruction input via said serial data input, loading predetermined identifying data characteristic of and stored within said integrated circuit into said first portion of said serial test scan chain, and serially outputting said identifying data via said serial data output from said first portion of said serial test scan chain; and (v) in response to said identifying-data-requesting-instruction connecting said first portion of said serial test scan chain between said serial data input and said serial data output and bypassing said second portion of the scan chain cells not within said first portion of said serial test scan chain.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-25 | 2001-11-24 | 2002-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-25 | 2005-11-24 | 2006-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-25 | 2009-11-24 | 2010-05-26 | $7700.00 | Window Closed / Lapsed |