Patent US5754080A successfully refreshed from Google Patents.
US5754080A
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Single-edge triggered phase detector
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1997-04-14
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Granted: 1998-05-19
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Expires: 2017-04-14
Abstract
Abstract A single-edge triggered phase detector which provides high speed phase detection. The phase detector works on only a single edge of the clock and data signal, which can be either the rising or falling edge. Extracted control signals are latched for at least one half of a clock period or more to ensure full rail to rail swing.
Inventors
- 👤 Dao-Long Chen
- 👤 Robert D. Waldron
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:52
CPC Classifications
H; H03; H03D; H03D13/00; H03D13/001; H03D13/002; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891
Claims Analysis
Total Claims: 50
Claim 1
Independent Claim
111 words
A method for adjusting a clock signal, comprising the steps of: detecting a unipolar transition on a data signal; detecting at least one unipolar transition on said clock signal; and adjusting said clock signal, in response to said detected data signal unipolar transition and said at least one detected clock signal unipolar transition, by a plurality of control signals comprising a first signal and a second signal different from the first signal, said first and second signals each having a minimum pulse width of at least one half clock period of the clock signal to phase lock a subsequent transition of the data signal and clock signal coincident with each other.
Claim 2
Independent Claim
111 words
A method for adjusting a clock signal, comprising the steps of: detecting a unipolar transition on a data signal; detecting at least one unipolar transition on said clock signal; and adjusting said clock signal, in response to said detected data signal unipolar transition and said at least one detected clock signal unipolar transition, by a plurality of control signals comprising a first signal and a second signal different from the first signal, said first and second signals each having a minimum pulse width of at least one half clock period of the clock signal to phase lock a subsequent transition of the data signal and clock signal coincident with each other.
Claim 3
Dependent Claim
16 words
The method of claim 1 wherein said clock signal is generated by a voltage controlled oscillator.
Claim 4
Dependent Claim
37 words
The method of claim 1 wherein the step of adjusting said clock signal comprises adjusting phase of said clock signal to phase lock the subsequent transition of the data signal and clock signal coincident with each other.
Claim 5
Independent Claim
115 words
A method for generating a plurality of controls signals used to adjust a clock signal, said plurality of control signals comprising a first signal and a second signal different from the first signal, comprising the steps of: detecting a unipolar transition on a data signal; detecting at least one unipolar transition on said clock signal; and generating said first and second control signals, each having a minimum pulse width of at least one half clock period of the clock signal, in response to said detected data signal unipolar transition and said at least one detected clock signal unipolar transition to synchronize a subsequent transition of the data signal and clock signal coincident with each other.
Claim 6
Independent Claim
115 words
A method for generating a plurality of controls signals used to adjust a clock signal, said plurality of control signals comprising a first signal and a second signal different from the first signal, comprising the steps of: detecting a unipolar transition on a data signal; detecting at least one unipolar transition on said clock signal; and generating said first and second control signals, each having a minimum pulse width of at least one half clock period of the clock signal, in response to said detected data signal unipolar transition and said at least one detected clock signal unipolar transition to synchronize a subsequent transition of the data signal and clock signal coincident with each other.
Claim 7
Dependent Claim
21 words
The method of claim 4 wherein said plurality of control signals minimizes phase difference between said data signal and clock signal.
Claim 8
Dependent Claim
26 words
The method of claim 4 wherein said plurality of control signals synchronize a subsequent transition of the data signal and clock signal coincident with each other.
Claim 9
Dependent Claim
20 words
The method of claim 4 wherein said plurality of control signals are used to adjust phase of said clock signal.
Claim 10
Independent Claim
159 words
A method for generating a plurality of control signals in a system having at least one data signal and at least one clock signal, said plurality of control signals comprising a first signal and a second signal different from the first signal, and said data and clock signals comprising a plurality of rising and falling edge transitions, comprising the steps of: detecting a single edge transition of said data signal; detecting a first single edge transition of said clock signal; detecting a second single edge transition, having a same polarity as the first single edge transition, of said clock signal; and generating said first and second control signals, each having a minimum pulse width of at least one half clock period of the clock signal, in response to said detected data signal transition and said detected first and second clock signal transitions, to phase lock a subsequent transition of the data signal and clock signal coincident with each other.
Claim 11
Independent Claim
159 words
A method for generating a plurality of control signals in a system having at least one data signal and at least one clock signal, said plurality of control signals comprising a first signal and a second signal different from the first signal, and said data and clock signals comprising a plurality of rising and falling edge transitions, comprising the steps of: detecting a single edge transition of said data signal; detecting a first single edge transition of said clock signal; detecting a second single edge transition, having a same polarity as the first single edge transition, of said clock signal; and generating said first and second control signals, each having a minimum pulse width of at least one half clock period of the clock signal, in response to said detected data signal transition and said detected first and second clock signal transitions, to phase lock a subsequent transition of the data signal and clock signal coincident with each other.
Claim 12
Dependent Claim
21 words
The method of claim 8 wherein said plurality of control signals minimizes phase difference between said data signal and clock signal.
Claim 13
Dependent Claim
26 words
The method of claim 8 wherein said plurality of control signals synchronize a subsequent transition of the data signal and clock signal coincident with each other.
Claim 14
Dependent Claim
20 words
The method of claim 8 wherein said plurality of control signals are used to adjust phase of said clock signal.
Claim 15
Independent Claim
91 words
A method for generating a plurality of control signals by a phase detector, comprising the steps of: activating a first control signal upon detection of a unipolar transition on a data signal; activating a second control signal and deactivating said first control signal upon detection by said phase detector of a unipolar transition on said clock signal, said phase detector having an input for directly receiving said clock signal; and deactivating said activated second control signal upon detection by said phase detector of a subsequent unipolar transition on said clock signal.
Claim 16
Independent Claim
91 words
A method for generating a plurality of control signals by a phase detector, comprising the steps of: activating a first control signal upon detection of a unipolar transition on a data signal; activating a second control signal and deactivating said first control signal upon detection by said phase detector of a unipolar transition on said clock signal, said phase detector having an input for directly receiving said clock signal; and deactivating said activated second control signal upon detection by said phase detector of a subsequent unipolar transition on said clock signal.
Claim 17
Dependent Claim
21 words
The method of claim 12 wherein said first and second control signals are used to adjust phase of said clock signal.
Claim 18
Independent Claim
83 words
A method for generating a plurality of control signals by a phase detector, comprising the steps of: latching a first control signal upon detection of an active data signal; latching a second control signal and resetting said first control signal upon detection by said phase detector of an active clock signal, said phase detector having an input for directly receiving said active clock signal; and resetting said latched second control signal upon detection by said phase detector of a subsequent active clock signal.
Claim 19
Independent Claim
83 words
A method for generating a plurality of control signals by a phase detector, comprising the steps of: latching a first control signal upon detection of an active data signal; latching a second control signal and resetting said first control signal upon detection by said phase detector of an active clock signal, said phase detector having an input for directly receiving said active clock signal; and resetting said latched second control signal upon detection by said phase detector of a subsequent active clock signal.
Claim 20
Dependent Claim
21 words
The method of claim 14 wherein said first and second control signals are used to adjust phase of said clock signal.
Claim 21
Dependent Claim
98 words
A phase detector, comprising: data means for detecting a unipolar transition on a data signal; clock means for detecting at least one unipolar transition on a clock signal; and means, coupled to said data means and said clock means, for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of the clock signal to phase lock a subsequent transition of the data signal and clock signal coincident with each other.
Claim 22
Dependent Claim
98 words
A phase detector, comprising: data means for detecting a unipolar transition on a data signal; clock means for detecting at least one unipolar transition on a clock signal; and means, coupled to said data means and said clock means, for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of the clock signal to phase lock a subsequent transition of the data signal and clock signal coincident with each other.
Claim 23
Dependent Claim
113 words
A phase locked loop circuit, comprising a voltage controlled oscillator and a phase detector, wherein said phase detector further comprises: data means for detecting a unipolar transition on a data signal; clock means for detecting at least one unipolar transition on a clock signal; and means, coupled to said data means and said clock means, for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of the clock signal, to synchronize a subsequent transition of the data signal and clock signal coincident with each other.
Claim 24
Dependent Claim
113 words
A phase locked loop circuit, comprising a voltage controlled oscillator and a phase detector, wherein said phase detector further comprises: data means for detecting a unipolar transition on a data signal; clock means for detecting at least one unipolar transition on a clock signal; and means, coupled to said data means and said clock means, for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of the clock signal, to synchronize a subsequent transition of the data signal and clock signal coincident with each other.
Claim 25
Dependent Claim
16 words
The circuit of claim 17 wherein said clock signal is generated by said voltage controlled oscillator.
Claim 26
Dependent Claim
22 words
The circuit of claim 18 further comprising a charge pump, wherein said plurality of control signals are coupled to the charge pump.
Claim 27
Dependent Claim
120 words
A phase locked loop circuit, comprising a phase detector, wherein said phase detector further comprises: data means for detecting a unipolar transition on a data signal; clock means for detecting at least one unipolar transition on a clock signal; means, coupled to said data means and said clock means, for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of the clock signal; and means, coupled to said plurality of control signals, for adjusting phase of said clock signal to coincide a subsequent data signal unipolar transition and clock signal unipolar transition.
Claim 28
Dependent Claim
120 words
A phase locked loop circuit, comprising a phase detector, wherein said phase detector further comprises: data means for detecting a unipolar transition on a data signal; clock means for detecting at least one unipolar transition on a clock signal; means, coupled to said data means and said clock means, for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of the clock signal; and means, coupled to said plurality of control signals, for adjusting phase of said clock signal to coincide a subsequent data signal unipolar transition and clock signal unipolar transition.
Claim 29
Dependent Claim
16 words
The circuit of claim 20 wherein said clock signal is generated by a voltage controlled oscillator.
Claim 30
Dependent Claim
22 words
The circuit of claim 21 further comprising a charge pump, wherein said plurality of control signals are coupled to said charge pump.
Claim 31
Independent Claim
96 words
A system for generating a plurality of control signals, comprising a phase detector circuit having an input for directly receiving a clock signal, said phase detector circuit comprising: means for activating a first control signal upon detection of a unipolar transition on a data signal; means for activating a second control signal, and deactivating said first control signal, upon detection by said phase detector of a unipolar transition on said clock signal; and means for deactivating said activated second control signal upon detection by said phase detector of a subsequent unipolar transition on said clock signal.
Claim 32
Independent Claim
96 words
A system for generating a plurality of control signals, comprising a phase detector circuit having an input for directly receiving a clock signal, said phase detector circuit comprising: means for activating a first control signal upon detection of a unipolar transition on a data signal; means for activating a second control signal, and deactivating said first control signal, upon detection by said phase detector of a unipolar transition on said clock signal; and means for deactivating said activated second control signal upon detection by said phase detector of a subsequent unipolar transition on said clock signal.
Claim 33
Dependent Claim
16 words
The system of claim 23 wherein said clock signal is generated by a voltage controlled oscillator.
Claim 34
Dependent Claim
18 words
The system of claim 24 wherein said plurality of control signals are coupled to said voltage controlled oscillator.
Claim 35
Dependent Claim
23 words
The system of claim 23 further comprising means, coupled to said first and second control signals, for adjusting phase of said clock signal.
Claim 36
Dependent Claim
94 words
A phase detector circuit for generating a plurality of control signals, said phase detector circuit having an input for directly receiving a clock signal, comprising: means for latching a first control signal upon detection of an active signal level of a data signal; means for latching a second control signal and resetting said first control signal upon detection by said phase detector circuit of an active signal level of said clock signal; and means for resetting said latched second control signal upon detection by said phase detector circuit of a subsequent active clock signal.
Claim 37
Dependent Claim
94 words
A phase detector circuit for generating a plurality of control signals, said phase detector circuit having an input for directly receiving a clock signal, comprising: means for latching a first control signal upon detection of an active signal level of a data signal; means for latching a second control signal and resetting said first control signal upon detection by said phase detector circuit of an active signal level of said clock signal; and means for resetting said latched second control signal upon detection by said phase detector circuit of a subsequent active clock signal.
Claim 38
Dependent Claim
16 words
The circuit of claim 27 wherein said clock signal is generated by a voltage controlled oscillator.
Claim 39
Dependent Claim
18 words
The circuit of claim 28 wherein said plurality of control signals are coupled to said voltage controlled oscillator.
Claim 40
Dependent Claim
23 words
The system of claim 27 further comprising means, coupled to said first and second control signals, for adjusting phase of said clock signal.
Claim 41
Dependent Claim
27 words
A method for using the phase detector of claim 16, comprising the step of using said plurality of control signals to adjust phase of said clock signal.
Claim 42
Dependent Claim
29 words
A method for using the phase lock loop circuit of claim 17, comprising the step of using said plurality of control signals to adjust phase of said clock signal.
Claim 43
Dependent Claim
109 words
A phase detector, comprising: a unipolar data signal transition detector circuit; a unipolar clock signal transition detector circuit for detecting a unipolar transition of said clock signal; a control signal generation circuit coupled to said unipolar data signal transition detector circuit and said unipolar clock signal transition detector circuit for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of said clock signal; and means for synchronizing a subsequent data signal transition and subsequent clock signal transition coincident with each other.
Claim 44
Dependent Claim
109 words
A phase detector, comprising: a unipolar data signal transition detector circuit; a unipolar clock signal transition detector circuit for detecting a unipolar transition of said clock signal; a control signal generation circuit coupled to said unipolar data signal transition detector circuit and said unipolar clock signal transition detector circuit for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of said clock signal; and means for synchronizing a subsequent data signal transition and subsequent clock signal transition coincident with each other.
Claim 45
Dependent Claim
123 words
A phase locked loop circuit, comprising a voltage controlled oscillator and a phase detector, wherein said phase detector further comprises: a unipolar data signal transition detector circuit; a unipolar clock signal transition detector circuit for detecting a unipolar transition of said clock signal; a control signal generation circuit coupled to said unipolar data signal transition detector circuit and said unipolar clock signal transition detector circuit for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of said clock signal; and means for synchronizing at least one subsequent data and clock signal coincident with each other.
Claim 46
Dependent Claim
123 words
A phase locked loop circuit, comprising a voltage controlled oscillator and a phase detector, wherein said phase detector further comprises: a unipolar data signal transition detector circuit; a unipolar clock signal transition detector circuit for detecting a unipolar transition of said clock signal; a control signal generation circuit coupled to said unipolar data signal transition detector circuit and said unipolar clock signal transition detector circuit for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of said clock signal; and means for synchronizing at least one subsequent data and clock signal coincident with each other.
Claim 47
Independent Claim
123 words
A method for adjusting a clock signal, comprising the steps of: detecting a unipolar transition on a data signal comprising a plurality of transitioning data values and a plurality of consecutive same value data values; detecting at least one unipolar transition on said clock signal; and adjusting said clock signal in response to said detected data signal unipolar transition and said detected clock signal unipolar transition by generating a first control signal having a fixed pulse width equal to a clock period of said clock signal and a second control signal having pulse width dependent upon the relative phase relationship between the data signal and clock signal, to synchronize a subsequent transition of the data signal and clock signal coincident with each other.
Claim 48
Independent Claim
123 words
A method for adjusting a clock signal, comprising the steps of: detecting a unipolar transition on a data signal comprising a plurality of transitioning data values and a plurality of consecutive same value data values; detecting at least one unipolar transition on said clock signal; and adjusting said clock signal in response to said detected data signal unipolar transition and said detected clock signal unipolar transition by generating a first control signal having a fixed pulse width equal to a clock period of said clock signal and a second control signal having pulse width dependent upon the relative phase relationship between the data signal and clock signal, to synchronize a subsequent transition of the data signal and clock signal coincident with each other.
Claim 49
Dependent Claim
115 words
A phase detector, comprising: data means for detecting a unipolar transition on a data signal comprising a plurality of transitioning data values and a plurality of consecutive same value data values; clock means for detecting a unipolar transition on said clock signal; and means, coupled to said data means and said clock means, for adjusting said clock signal by generating a first control signal having a fixed pulse width equal to a clock period of said clock signal and a second control signal having pulse width dependent upon the relative phase relationship between the data signal and clock signal, to synchronize a subsequent transition of the data signal and clock signal coincident with each other.
Claim 50
Dependent Claim
115 words
A phase detector, comprising: data means for detecting a unipolar transition on a data signal comprising a plurality of transitioning data values and a plurality of consecutive same value data values; clock means for detecting a unipolar transition on said clock signal; and means, coupled to said data means and said clock means, for adjusting said clock signal by generating a first control signal having a fixed pulse width equal to a clock period of said clock signal and a second control signal having pulse width dependent upon the relative phase relationship between the data signal and clock signal, to synchronize a subsequent transition of the data signal and clock signal coincident with each other.
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