Clock generating circuit for asynchronous pulses

Claim 2

A circuit for generating clock and control signals from first and second asynchronous binary signals, comprising: first means for generating first and second pulse signals responsive to said first and second asynchronous binary signals; second means connected to said first means for generating a clock pulse signal responsive to said first or second pulse signal; and third means connected to said first and second means for generating an identification control signal to indicate which of said first or second binary signals is first received by said circuit.

Claim 3

The circuit of claim 1, further comprising: fourth means connected to said first and second means responsive to said first and second pulse signals for generating an overlap control signal to indicate overlap in the first and second pulse signals.

Claim 4

The circuit of claim 1 wherein said first means includes: a first D-type flip-flop for receiving said first asynchronous binary signal on an input thereof and for providing said first pulse signal on an output thereof; and a second D-type flip-flop for receiving said second asynchronous binary signal on an input thereof and for providing said second pulse signal on an output thereof.

Claim 5

The circuit of claim 3 wherein said first means further includes: a first feedback loop connected between an inverted output and a reset input of said first flip-flop; and a second feedback loop connected between an inverted output and a reset input of said second flip-flop.

Claim 6

The circuit of claim 4 wherein each of said first and second feedback loops includes a delaying circuit series connected with a coincidence gate.

Claim 7

The circuit of claim 5 wherein said coincidence gates are two input AND gates each having an input for receiving an externally generated reset signal and another input connected to an output of its respective delaying circuit.

Claim 8

The circuit of claim 6 wherein said externally generated reset signal is an active low signal.

Claim 9

The circuit of claim 1 wherein said second means includes: a two input OR gate for receiving said first and second pulse signals; and a pulse shaping circuit, SR latch, and a clocked SR latch series connected between the output of said OR gate and an output of said second means which provides said clock signal.

Claim 10

The circuit of claim 8 wherein said pulse shaping circuit is effective for transferring a low going signal from the OR gate output directly to said SR type latch and for delaying the transfer of a high going signal from the OR gate output to said SR latch.

Claim 11

The circuit of claim 9 wherein said pulse shaping circuit includes: a first AND gate having an output and having inputs connected to the output of said OR gate; a delaying circuit having an input connected to the output of said first AND gate and having an output; a second AND gate having inputs connected to the outputs of said first AND gate and said delaying circuit; and a third AND gate having inputs connected to the OR gate output and the outputs of said first and second AND gates, respectively, and having an output connected to a set input of said SR latch, and having an inverted output connected to a reset input of said SR latch.

Claim 12

The circuit of claim 8 wherein said second means further includes: a reset circuit having a first input connected to an inverted output of said SR latch, and second and third inputs for receiving said clock signal and an externally generated reset signal, respectively, said reset circuit further having an output connected to a reset input of said clocked SR latch.

Claim 13

The circuit of claim 11 wherein said reset circuit includes: a two input NAND gate and a two input AND gate, with said first and second inputs connected to the inputs of said NAND gate, said third input and the output of said NAND gate connected to the inputs of said AND gate, and the output of said AND gate connected to the reset input of said clocked SR latch.

Claim 14

The circuit of claim 1 wherein said third means includes: a two input NAND gate and an SR latch with a first input of said NAND gate connected to said first means and a second input receiving said clock signal, the output of said NAND gate connected to the reset input of said SR latch and said first input connected to the set input of said SR latch.

Claim 15

The circuit of claim 13 wherein said identification control signal is provided by an inverted output of said SR latch.

Claim 16

The circuit of claim 14 wherein the first input of said NAND gate receives a delayed and inverted version of said first pulse signal.

Claim 17

The circuit of claim 2 wherein said fourth means includes: a NAND gate for receiving said first and second pulse signals; a pulse shaping circuit having an input connected to the output of said NAND gate; first and second clocked SR latches, each having a set input connected to the output of said pulse shaping circuit; and a first AND gate having inputs connected to inverted outputs of said first and second latches and providing said overlap control signal at an output thereof.

Claim 18

The circuit of claim 16 wherein said pulse shaping circuit includes: a second AND gate having inputs connected to the output of said NAND gate; a delaying circuit having an input connected to the output of said second AND gate; a third AND gate connected to outputs of said delaying circuit and said second AND gate; and a fourth AND gate having inputs connected to outputs of said NAND gate and said second and third AND gates, respectively.

Claim 19

The circuit of claim 16 wherein the clock input of said first latch receives said first pulse signal and the clock input of said second latch receives said second pulse signal.

Claim 20

The circuit of claim 18 further comprising: an OR gate for receiving said first and second pulse signals; a delaying circuit having an input connected to the output of said OR gate; and a second AND gate having two inputs connected to the output of said OR gate and said delayed output, respectively, and having an output connected to a reset input on each of said first and second latches.

Claim 21

A circuit for generating clock and control signals from first and second asynchronous binary signals, comprising: first means for generating first and second pulse signals responsive to said first and second asynchronous binary signals; second means connected to said first means for generating a clock pulse signal responsive to said first or second pulse signal, said second means including: a two input OR gate for receiving said first and second pulse signals; a first pulse shaping circuit, a first SR latch, and a first clocked SR latch series connected between the output of said OR gate and an output which provides said clock signal; and a reset circuit having a first input connected to an inverted output of said first SR latch, and second and third inputs for receiving said clock signal and an externally generated reset signal, respectively, said reset circuit further having an output connected to a reset input of said first clocked SR latch; third means connected to said first and second means for generating an identification control signal to indicate which of said first or second binary signals is first received by said circuit; and fourth means connected to said first and second means responsive to said first and second pulse signals for generating an overlap control signal to indicate overlap in the first and second pulse signals.

Claim 22

A circuit for generating clock and control signals from first and second asynchronous binary signals, comprising: first means for generating first and second pulse signals responsive to said first and second asynchronous binary signals; second means connected to said first means for generating a clock pulse signal responsive to said first or second pulse signal, said second means including: a two input OR gate for receiving said first and second pulse signals; a first pulse shaping circuit, a first SR latch, and a first clocked SR latch series connected between the output of said OR gate and an output which provides said clock signal; and a reset circuit having a first input connected to an inverted output of said first SR latch, and second and third inputs for receiving said clock signal and an externally generated reset signal, respectively, said reset circuit further having an output connected to a reset input of said first clocked SR latch; third means connected to said first and second means for generating an identification control signal to indicate which of said first or second binary signals is first received by said circuit; and fourth means connected to said first and second means responsive to said first and second pulse signals for generating an overlap control signal to indicate overlap in the first and second pulse signals.

Claim 23

The circuit of claim 20 wherein said first means includes: a first D-type flip-flop for receiving said first asynchronous binary signal on an input thereof and for providing said first pulse signal on an output thereof; and a second D-type flip-flop for receiving said second asynchronous binary signal on an input thereof and for providing said second pulse signal on an output thereof.

Claim 24

The circuit of claim 21 wherein said third means includes: a first NAND gate and a second SR latch, with a first input of said NAND gate connected to said first means and a second input receiving said clock signal, the output of said NAND gate connected to the reset input of said second SR latch, and the first input of said NAND gate connected to the set input of said second SR latch.

Claim 25

The circuit of claim 22 wherein said fourth means includes: a second NAND gate for receiving said first and second pulse signals; a second pulse shaping circuit having an input connected to the output of said second NAND gate; second and third clocked SR latches each having a set input connected to the output of said second pulse shaping circuit; and a first AND gate having inputs connected to inverted outputs of said second and third clocked SR latches and providing said overlap control signal at an output thereof.

Claim 26

The circuit of claim 23 wherein said second pulse shaping circuit includes: a second AND gate having inputs connected to the output of said second NAND gate; a delaying circuit having an input connected to the output of said second AND gate; a third AND gate connected to outputs of said delaying circuit and said second AND gate; and a fourth AND gate having inputs connected to outputs of said NAND gate and said second and third AND gates, respectively.

Claim 27

The circuit of claim 23 wherein said first means further includes: a first feedback loop connected between an inverted output and a reset input of said first flip-flop; and a second feedback loop connected between an inverted output and a reset input of said second flip-flop; wherein said first feedback loop includes a first delaying circuit series connected with a second AND gate and said second feedback loop includes a second delaying circuit series connected with a third AND gate; wherein each of said first and second feedback loops includes a delaying circuit series connected with a coincidence gate; and wherein each of said second and third AND gates has an input for receiving an externally generated reset signal and another input connected to an output of its respective delaying circuit.

Claim 28

The circuit of claim 25 wherein said first pulse shaping circuit of said second means includes: a fourth AND gate having inputs connected to the output of said OR gate; a third delaying circuit having an input connected to the output of said fourth AND gate and having an output; a fifth AND gate having inputs connected to the outputs of said fourth AND gate and said third delaying circuit; and a sixth AND gate having inputs connected to the OR gate output and the outputs of said fourth and fifth AND gates, respectively, and having an output connected to a set input of said first SR latch, and having an inverted output connected to a reset input of said first SR latch.

Claim 29

The circuit of claim 26 wherein said reset circuit of said second means includes: a third NAND gate and a seventh AND gate, with the first and second inputs of said reset circuit connected to the inputs of said third NAND gate, said third input of said reset circuit and the output of said third NAND gate connected to the inputs of said seventh AND gate, and the output of said seventh AND gate connected to the reset input of said first clocked SR latch.

Claim 30

The circuit of claim 27 wherein said identification control signal is provided by an inverted output of said second SR latch, and wherein the first input of said first NAND gate is connected to the output of the delaying circuit in said first feedback loop.

Claim 31

The circuit of claim 28 wherein the clock input of said second clocked SR latch receives said first pulse signal and the clock input of said third clocked SR latch receives said second pulse signal, and wherein the output of said first pulse shaping circuit is connected to a reset input on each of said second and third clocked SR latches.