US5059833A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase detector suitable for use in phase lock loop
Assignee: NEC Corp
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Filing: 1990-10-17
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Granted: 1991-10-22
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Expires: 2010-10-17
Abstract
Abstract A digital phase detector comprises a first input for receiving an output of a voltage controlled oscillator and a second input for receiving a reference signal. When a phase of the first input is in advance of that of the second input or when a frequency of the first input is higher than that of the second input, the phase detector operates to output a first control signal for decrease of an oscillation frequency of the voltage controlled oscillator. When the phase of the first input is delayed from that of the second input or when the frequency of the first input is lower than that of the second input, the phase detector operates to output a second control signal for increase of the oscillation frequency of the voltage controlled oscillator. In addition, the phase detector is configured to output neither the first control signal nor the second control signal when both of the first input and the second input are at a low level.
Inventors
- 👤 Takashi Fujii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:56
CPC Classifications
H; H03; H03D; H03D13/00; H03D13/003; H03D13/004
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
399 words
A digital phase detector comprising a first input for receiving an output of a voltage controlled oscillator and a second input for receiving a reference signal, the phase detector operating to compare said first input with said second input both in phase and in frequency so as to output a first control signal for decrease of an oscillation frequency of the voltage controlled oscillatior when a phase of said first input is in advance of that of said second input or when a frequency of said first input is higher than that of said second input, and so as to output a second control signal for increase of the oscillation frequency of the voltage controlled oscillator when the phase of said first input is delayed from that of said second input or when the frequency of said first input is lower than that of said second input, the phase detector being configured to output neither said first control signal nor said second control signal when both of said first input and said second input are at a low level; said digital phase detector further including: first and second three-input NAND gates each having a first input connected to receive said output of the voltage controlled oscillator and a second input connected to receive said reference signal; a first RS-flipflop having a set input connected to receive said output of the voltage controlled oscillator, a reset input connected to an output of said first NAND gate, and a Q output connected to a third input of said second NAND gate; a second RS-flipflop having a set input connected to receive said reference signal, a reset input connected to an output of said second NAND gate, and a Q output connected to a third input of said first NAND gate; a first logic output circuit having a first input connected to a Q output of said first flipflop, a second input connected to the Q output of said second flipflop, and an output for generating said first control signal for decrease of the oscillaiton frequency of the voltage controlled oscillator; and a second logic output circuit having a first input connected to a Q output of said second flipflop, a second input connected to the Q output of said first flipflop, and an output for generating said second control signal for increase of the oscillation frequency of the voltage controlled oscillator.
Claim 2
Dependent Claim
399 words
A digital phase detector comprising a first input for receiving an output of a voltage controlled oscillator and a second input for receiving a reference signal, the phase detector operating to compare said first input with said second input both in phase and in frequency so as to output a first control signal for decrease of an oscillation frequency of the voltage controlled oscillatior when a phase of said first input is in advance of that of said second input or when a frequency of said first input is higher than that of said second input, and so as to output a second control signal for increase of the oscillation frequency of the voltage controlled oscillator when the phase of said first input is delayed from that of said second input or when the frequency of said first input is lower than that of said second input, the phase detector being configured to output neither said first control signal nor said second control signal when both of said first input and said second input are at a low level; said digital phase detector further including: first and second three-input NAND gates each having a first input connected to receive said output of the voltage controlled oscillator and a second input connected to receive said reference signal; a first RS-flipflop having a set input connected to receive said output of the voltage controlled oscillator, a reset input connected to an output of said first NAND gate, and a Q output connected to a third input of said second NAND gate; a second RS-flipflop having a set input connected to receive said reference signal, a reset input connected to an output of said second NAND gate, and a Q output connected to a third input of said first NAND gate; a first logic output circuit having a first input connected to a Q output of said first flipflop, a second input connected to the Q output of said second flipflop, and an output for generating said first control signal for decrease of the oscillaiton frequency of the voltage controlled oscillator; and a second logic output circuit having a first input connected to a Q output of said second flipflop, a second input connected to the Q output of said first flipflop, and an output for generating said second control signal for increase of the oscillation frequency of the voltage controlled oscillator.
Claim 3
Dependent Claim
124 words
A digital phase detector claimed in claim 1 wherein said first logic output circuit is composed of a first NOR gate having a first input connected to the Qoutput of said first flipflop, a second input connected to the Q output of said second flipflop, and an output for generating said first control signal for decrease of the oscillation frequency of the voltage controlled oscillator; and wherein said second logic output circuit is composed of a second NOR gate having a first input connected to the Q output of said second flipflop, a second input connected to the Q output of said first flipflop, and an output for generating said second control signal for increase of the oscillation frequency of the voltage controlled oscillator.
Claim 4
Dependent Claim
162 words
A digital phase detector claimed in claim 1 wherein said first logic output circuit is composed of a first two-input NAND gate having a first input connected to the Qoutput of said first flipflop and a second input connected to the Q output of said second flipflop, and a first inverter having an input connected to an output of said first two-input NAND gate and an output for generating said first control signal for decrease of the oscillation frequency of the voltage controlled oscillator; and wherein said second logic output circuit is composed of a second two-input NAND gate having a first input connected to the Q output of said second flipflop and a second input connected to the Q output of said first flipflop, and a second inverter having an input connected to an output of said second two-input NAND gate and an output for generating said second control signal for increase of the oscillation frequency of the voltage controlled oscillator.
Claim 5
Dependent Claim
237 words
A digital phase detector comprising: a first input for receiving an output of a voltage controlled oscillator; a second input for receiving a reference signal; first and second three-input NAND gates each having a first input connected to receive said output of the voltage controlled oscillator and a second input connected to receive said reference signal; a first RS-flipflop having a set input connected to receive said output of the voltage controlled oscillator, a reset input connected to an output of said first NAND gate, and a Q output connected to a third input of said second NAND gate; a second RS-flipflop having a set input connected to receive said reference signal, a reset input connected to an output of said second NAND gate, and a Q output connected to a third input of said first NAND gate; a first logic output circuit having a first input connected to a Q output of said first flipflop, a second input connected to the Q output of said second flipflop, and an output for generating a DOWN signal for decrease of the oscillation frequency of the voltage controlled oscillator; and a second logic output circuit having a first input connected to a Q output of said second flipflop, a second input connected to the Q output of said first flipflop, and an output for generating an UP signal for increase of the oscillation frequency of the voltage controlled oscillator.
Claim 6
Dependent Claim
237 words
A digital phase detector comprising: a first input for receiving an output of a voltage controlled oscillator; a second input for receiving a reference signal; first and second three-input NAND gates each having a first input connected to receive said output of the voltage controlled oscillator and a second input connected to receive said reference signal; a first RS-flipflop having a set input connected to receive said output of the voltage controlled oscillator, a reset input connected to an output of said first NAND gate, and a Q output connected to a third input of said second NAND gate; a second RS-flipflop having a set input connected to receive said reference signal, a reset input connected to an output of said second NAND gate, and a Q output connected to a third input of said first NAND gate; a first logic output circuit having a first input connected to a Q output of said first flipflop, a second input connected to the Q output of said second flipflop, and an output for generating a DOWN signal for decrease of the oscillation frequency of the voltage controlled oscillator; and a second logic output circuit having a first input connected to a Q output of said second flipflop, a second input connected to the Q output of said first flipflop, and an output for generating an UP signal for increase of the oscillation frequency of the voltage controlled oscillator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-21 | 1995-04-22 | 1995-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-21 | 1999-04-22 | 1999-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-21 | 2003-04-22 | 2003-10-22 | $7700.00 | Window Closed / Lapsed |