Self-aligned source/drain mask ROM memory cell using trench etched channel

Claim 2

A plurality of semiconductor memory devices on a silicon semiconductor substrate said devices having vertical channels comprising: a plurality of trenches in the surface of said silicon semiconductor substrate, said trenches having sidewalls in which channel regions are located, ion implanted source and drain regions in said substrate doped with an N type dopant self-aligned with said trenches with said source regions and said drain regions formed in said substrate, said source regions located below said trenches and said drain regions juxtaposed with and located between said trenches, said channel regions formed in said substrate between said trenches below said drain regions, a dielectric layer over said source/drain regions, a conductive word-line over said dielectric layer extending continuously across a said drain region down into a said trench extending across said source regions and across a next one of said drain regions and extending down into a next one of said said trenches and crossing a following one of said source regions, and a ROM code program implant region in one of said channels in the sidewall between one of said source regions and one of said drain regions adjacent thereto, said ROM code program implant region having been ion implanted with a dose of boron through said conductive word-line into one of said channel regions in said device in a selected region of said device.

Claim 3

The device of claim 1, wherein said device comprises a source/drain mask ROM memory cell with a trench etched channel said ROM code program implant region having been ion implanted with a dose of boron P type dopant from about 1E13 cm -2 to about 5E13 cm -2 at an energy from about 180 keV to about 300 KeV.

Claim 4

The device of claim 1, wherein said source/drain regions comprise regions implanted with dopant selected from the group consisting of arsenic, phosphorus and antimony with a dose from about 1E15 cm -2 to about 6E15 cm -2 which was implanted at an energy from about 30 keV to about 60 keV, and annealed into said silicon semiconductor substrate.

Claim 5

The device of claim 1, wherein source regions extend across beneath said trenches and said drain regions are juxtaposed with said trenches above the ends of said source regions.

Claim 6

The device of claim 1, comprising a flat structure.

Claim 7

The device of claim 5, wherein said flat structure includes no field oxide structures.

Claim 8

The device of claim 1, including: a doped contact region in said substrate including a buried source region adjacent to one of said channel regions and and overlapping a said source region with a metal contact formed on the surface of said doped contact region, and means for reading a cell, including a bit-line, word-line, source (n, m, n-1) a cell is selected as shown in the following Table: ______________________________________ Bitline Source Wordline ______________________________________ Selected 2.0 V Ground Vcc Unselected sharing 2.0 V Float Vcc same bit-line and word-line Unselected others Float or Ground Float or Ground Ground ______________________________________

Claim 9

A plurality of semiconductor memory devices on a silicon semiconductor substrate said devices having vertical channels comprising: trenches in the surface of said silicon semiconductor substrate, said trenches having sidewalls in which channel regions are located, said trenches including bases in said substrate, and said substrate having upper surfaces between and/or side from said trenches. source dopant and drain dopant which has been ion implanted into said bases and said upper surfaces of said substrate and annealed to form N-type source and drain regions in said silicon semiconductor substrate with said source regions and said drain regions formed in said substrate with said source regions located below said trenches and said drain regions juxtaposed with and between said trenches with said channel regions formed between said trenches and below said drain regions, a metal deposited on the surface of said source/drain regions having been annealed into a metal silicide in said source regions and said drain regions, a gate oxide layer formed over said device covering said source regions and said drain regions, and a conductive word-line formed over said second dielectric layer extending continuously across a said drain region and extending down into one of said trenches crossing a said source region continuing across a next one of said drain regions and extending down into a next one of said said trenches and across the next one of said source regions, and a ROM code program implant region in one of said channels in the sidewall between one of said source regions and one of said drain regions adjacent thereto, said ROM code program implant region having been ion implanted with a dose of boron through said conductive word-line into one of said channel regions in said device in a selected region of said device.

Claim 10

A plurality of semiconductor memory devices on a silicon semiconductor substrate said devices having vertical channels comprising: trenches in the surface of said silicon semiconductor substrate, said trenches having sidewalls in which channel regions are located, said trenches including bases in said substrate, and said substrate having upper surfaces between and/or side from said trenches. source dopant and drain dopant which has been ion implanted into said bases and said upper surfaces of said substrate and annealed to form N-type source and drain regions in said silicon semiconductor substrate with said source regions and said drain regions formed in said substrate with said source regions located below said trenches and said drain regions juxtaposed with and between said trenches with said channel regions formed between said trenches and below said drain regions, a metal deposited on the surface of said source/drain regions having been annealed into a metal silicide in said source regions and said drain regions, a gate oxide layer formed over said device covering said source regions and said drain regions, and a conductive word-line formed over said second dielectric layer extending continuously across a said drain region and extending down into one of said trenches crossing a said source region continuing across a next one of said drain regions and extending down into a next one of said said trenches and across the next one of said source regions, and a ROM code program implant region in one of said channels in the sidewall between one of said source regions and one of said drain regions adjacent thereto, said ROM code program implant region having been ion implanted with a dose of boron through said conductive word-line into one of said channel regions in said device in a selected region of said device.

Claim 11

The device of claim 8, wherein source regions extend across beneath said trenches and said drain regions are juxtaposed with said trenches above the ends of said source regions.

Claim 12

The device of claim 9 wherein said metal comprises cobalt.

Claim 13

The device of claim 8, wherein metal deposited on the surface of said source and drain regions has been annealed into a metal silicide in said source/drain regions, and said source and drain regions are implanted with dopant selected from the group consisting of arsenic, phosphorus and antimony with from about 1E15 cm -2 to about 6E15 cm -2 which was implanted at an energy from about 30 keV to about 60 keV, and annealed into said silicon semiconductor substrate.

Claim 14

The device of claim 8, wherein source regions extend across beneath the base of said trenches and said drain regions extend across beneath said upper surfaces, said drain regions being juxtaposed with said trenches above the ends of said source regions.

Claim 15

The device of claim 8, wherein said device comprises a source/drain mask ROM memory cell with a trench etched channel said ROM code program implant region having been ion implanted with a dose of boron P type dopant from about 1E1 cm -2 to about 5E13 cm -2 at an energy from about 180 keV to about 300 keV.

Claim 16

The device of claim 8 including: a doped contact region in said substrate including a buried source region adjacent to one of said channel regions and and overlapping a said source region with a metal contact formed on the surface of said doped contact region, and means for reading a cell, including a bit-line, word-line, source (n, m, n-1) a cell is selected as shown in the following Table: ______________________________________ Bitline Source Wordline ______________________________________ Selected 2.0 V Ground Vcc Unselected sharing 2.0 V Float Vcc same bit-line and word-line Unselected others Float or Ground Float or Ground Ground ______________________________________

Claim 17

A plurality of semiconductor memory devices on a silicon semiconductor substrate said devices having vertical channels comprising: a plurality of trenches in the surface of said silicon semiconductor substrate, said trenches having sidewalls in which channel regions are located, ion implanted source regions and drain regions in said substrate self-aligned with said trenches with said source regions formed in said substrate below said trenches and said drain regions formed on the surface of said substrate between said trenches with said channel regions formed below said drain regions between said trenches, said source regions and said drain regions doped with a dopant selected from the group consisting of arsenic, phosphorus and antimony, a dielectric layer formed over said source regions and over said drain regions, a conductive word-line over said dielectric layer extending across a said drain region and down into a said trench and across a said source region and successively across the next ones of said drain and source regions, and a ROM code program implant region in one of said channels including the sidewall between one of said source regions and one of said drain regions adjacent thereto, said program implant region having been ion implanted with through said conductive word-line into one of said channel regions in said device between a said source region and a said drain region in a selected region of said device.

Claim 18

A plurality of semiconductor memory devices on a silicon semiconductor substrate said devices having vertical channels comprising: a plurality of trenches in the surface of said silicon semiconductor substrate, said trenches having sidewalls in which channel regions are located, ion implanted source regions and drain regions in said substrate self-aligned with said trenches with said source regions formed in said substrate below said trenches and said drain regions formed on the surface of said substrate between said trenches with said channel regions formed below said drain regions between said trenches, said source regions and said drain regions doped with a dopant selected from the group consisting of arsenic, phosphorus and antimony, a dielectric layer formed over said source regions and over said drain regions, a conductive word-line over said dielectric layer extending across a said drain region and down into a said trench and across a said source region and successively across the next ones of said drain and source regions, and a ROM code program implant region in one of said channels including the sidewall between one of said source regions and one of said drain regions adjacent thereto, said program implant region having been ion implanted with through said conductive word-line into one of said channel regions in said device between a said source region and a said drain region in a selected region of said device.

Claim 19

The device of claim 15, wherein: said source regions are formed in said trenches, said drain regions are formed on the surface of said substrate juxtaposed with and between said trenches with said channel regions therebetween, said source/drain regions doped with a dose of dopant selected from the group consisting of arsenic, phosphorus and antimony with a dose from about 1E15 cm -2 to about 6E15 cm -2 at an energy from about 30 keV to about 60 keV.

Claim 20

The device of claim 16, wherein: said program implant region has been ion implanted with a dose of boron from about 1E13 cm -2 to about 5E13 cm -2 at an energy from about 180 keV to about 300 keV through said conductive word-line into one of said channel regions in said device between a said source region and a said drain region in a selected region of said device.

Claim 21

The device of claim 15, including: metal deposited on the surface of said source/drain regions having been annealed into a metal silicide in said source/drain regions. said source regions are formed in said trenches, said drain regions are formed on the surface of said substrate juxtaposed with and between said trenches with said channel regions therebtween, said source/drain regions doped with a dose of dopant selected from the group consisting of arsenic, phosphorus and antimony with a dose from about 8E14 cm -2 to about 4E15 cm -2 at an energy from about 30 keV to about 60 keV.

Claim 22

The device of claim 18, wherein: said program implant region was ion implanted with a dose of boron from about 1E13 cm -2 to about 5E13 cm -2 at an energy from about 180 keV to about 300 keV through said conductive word-line into one of said channel regions in said device between a said source region and a said drain region in a selected region of said device.

Claim 23

The device of claim 15, including: doped contact region in said substrate including a buried source region adjacent to one of said channel regions and and overlapping a said source region with a metal contact formed on the surface of said doped contact region, and means for reading a cell, including a bit-line, word-line, source (n, m, n-1)a cell is selected as shown in the following Table: ______________________________________ Bitline Source Wordline ______________________________________ Selected 2.0 V Ground Vcc Unselected sharing 2.0 V Float Vcc same bit-line and word-line Unselected others Float or Ground Float or Ground Ground ______________________________________