Mask ROM device having highly integrated memory cell structure

Claim 1

A mask ROM device, comprising: a semiconductor substrate having a main surface; a plurality of recesses formed on the main surface of said semiconductor substrate, extending parallel to each other; a first MOS transistor train in which a plurality of MOS transistors connected in series are disposed in a direction crossing the direction in which said recesses extend; a second MOS transistor train disposed parallel to said first MOS transistor train including a plurality of MOS transistors connected in series; an isolating and insulating region formed between said first MOS transistor train and said second MOS transistor train for insulating and isolating said MOS transistors of said first MOS transistor train and the MOS transistors of said second MOS transistor train from each other; a bit line connected to the source/drain of the MOS transistor at one end of said first MOS transistor train and the source/drain of the MOS transistor at one end of said second MOS transistor train; and a source line connected to the source/drain of the MOS transistor at the other end of said first MOS transistor train and the source/drain of the MOS transistor at the other end of said second MOS transistor train, said MOS transistors included in said first MOS transistor train and second MOS transistor train including; a pair of source and drain formed at a bottom of said recess and on the main surface of said semiconductor substrate and aligned with said recess, a channel region formed in an inner surface of said recess positioned between said pair of source and drain, and a gate electrode formed on the inner surface of said recess with in insulating layer therebetween.