Counter having programmable periods and method therefor

Claim 2

A programmable counter comprising: a counter stage for receiving a clock signal, and a count enable signal, and producing a count value, wherein the counter stage increments the count value on an active clock edge when the count enable signal is active; a stall stage for receiving a stall enable signal, the clock signal, and coupled to the counter stage to provide the count enable signal, wherein the stall stage disables the count enable signal based on the stall enable signal; and a stall programmer stage for receiving a stall value, coupled to the counter stage for receiving the count value, and coupled to the stall stage for providing the stall enable signal, wherein the stall enable signal is asserted based on the stall value.

Claim 3

The programmable counter of claim 1, wherein the stall value indicates a rate for providing an active stall enable signal.

Claim 4

The programmable counter of claim 1, wherein the stall stage disables the count enable signal for an integer number of clock signal cycles.

Claim 5

The programmable counter of claim 1, wherein the stall stage disables the count enable signal for N contiguous clock signal cycles out of a total of M contiguous clock signal cycles.

Claim 6

The programmable counter of claim 4, wherein N is the integer 1, and M is an integer 2.

Claim 7

The programmable counter of claim 1, wherein the count value is a binary count value.

Claim 8

The programmable counter of claim 6 further comprising: a Gray code stage coupled to receive the count value, and providing Gray code value, wherein the Gray code value is one of a plurality of a Gray code sequence values based on the count value; wherein the stall programmer stage is coupled to the Gray code stage to receive the Gray code value.

Claim 9

The programmable counter of claim 1 further comprising: a multiplexer stage for receiving the count value having a plurality of bits, and providing a divided clock signal, wherein the divided clock signal is a representation of one of the plurality of bits.

Claim 10

The programmable counter of claim 8 wherein the divided clock is capable of representing a non-integer division of the clock signal.

Claim 13

The method of claim 10, further comprising the steps of: receiving the stall signal, wherein the stall signal provides a plurality of stall bits, each of the plurality of stall bits having a stall enable state indicator, wherein each of the plurality of stall bits has a corresponding counter value bit; and generating a stall enable signal based on the stall enable state indicator of a one of the plurality of stall bits, wherein the one of the plurality of stall bits is selected based on its corresponding counter value bit.

Claim 14

A phase locked loop comprising: a controllable frequency oscillator for receiving a phase correction signal, and providing an output frequency based on the phase correction signal; a phase comparator for receiving a reference signal having a reference phase, and a divided frequency signal having a divided phase, the phase comparator coupled to the controllable frequency oscillator for providing a phase correction signal based on the reference phase and the divided phase; a frequency divider coupled to the controllable frequency oscillator for receiving the output frequency, and coupled to the phase comparator for providing a divided frequency signal, wherein the divided frequency signal represents the output frequency divided by a divisor which can include a non-integer value, the frequency divider comprising: a counter stage for receiving a clock signal, and a count enable signal, and producing a count value, wherein the counter stage increments the count value on an active clock edge when the count enable signal is active; a stall stage for receiving a stall enable signal, the clock signal, and coupled to the counter stage to provide the count enable signal, wherein the stall stage disables the count enable signal based on the stall enable signal; and a stall programmer stage for receiving a stall value, coupled to the counter stage for receiving the count value, and coupled to the stall stage for providing the stall enable signal, wherein the stall enable signal is asserted based on the stall value.

Claim 15

A phase locked loop comprising: a controllable frequency oscillator for receiving a phase correction signal, and providing an output frequency based on the phase correction signal; a phase comparator for receiving a reference signal having a reference phase, and a divided frequency signal having a divided phase, the phase comparator coupled to the controllable frequency oscillator for providing a phase correction signal based on the reference phase and the divided phase; a frequency divider coupled to the controllable frequency oscillator for receiving the output frequency, and coupled to the phase comparator for providing a divided frequency signal, wherein the divided frequency signal represents the output frequency divided by a divisor which can include a non-integer value, the frequency divider comprising: a counter stage for receiving a clock signal, and a count enable signal, and producing a count value, wherein the counter stage increments the count value on an active clock edge when the count enable signal is active; a stall stage for receiving a stall enable signal, the clock signal, and coupled to the counter stage to provide the count enable signal, wherein the stall stage disables the count enable signal based on the stall enable signal; and a stall programmer stage for receiving a stall value, coupled to the counter stage for receiving the count value, and coupled to the stall stage for providing the stall enable signal, wherein the stall enable signal is asserted based on the stall value.

Claim 16

A pulse width modulator system comprising: a pulse width modulator for receiving a divided clock signal, and providing an output signal having an output clock period and an output clock duty cycle, wherein the clock period is controlled by a frequency of the divided clock signal; a frequency divider for receiving a system clock, and coupled to the pulse width modulator for providing the divided clock signal, wherein the divided clock signal represents the system clock signal divided by a divisor which can include a non-integer value, the frequency divider comprising: a counter stage for receiving a clock signal, and a count enable signal, and producing a count value, wherein the counter stage increments the count value on an active clock edge when the count enable signal is active; a stall stage for receiving a stall enable signal, the clock signal, and coupled to the counter stage to provide the count enable signal, wherein the stall stage disables the count enable signal based on the stall enable signal; and a stall programmer stage for receiving a stall value, coupled to the counter stage for receiving the count value, and coupled to the stall stage for providing the stall enable signal, wherein the stall enable signal is asserted based on the stall value.

Claim 17

A pulse width modulator system comprising: a pulse width modulator for receiving a divided clock signal, and providing an output signal having an output clock period and an output clock duty cycle, wherein the clock period is controlled by a frequency of the divided clock signal; a frequency divider for receiving a system clock, and coupled to the pulse width modulator for providing the divided clock signal, wherein the divided clock signal represents the system clock signal divided by a divisor which can include a non-integer value, the frequency divider comprising: a counter stage for receiving a clock signal, and a count enable signal, and producing a count value, wherein the counter stage increments the count value on an active clock edge when the count enable signal is active; a stall stage for receiving a stall enable signal, the clock signal, and coupled to the counter stage to provide the count enable signal, wherein the stall stage disables the count enable signal based on the stall enable signal; and a stall programmer stage for receiving a stall value, coupled to the counter stage for receiving the count value, and coupled to the stall stage for providing the stall enable signal, wherein the stall enable signal is asserted based on the stall value.