Fifty percent duty cycle divided-by-m counter

Claim 1

A divide-by-m counter for generating an output clock signal from a source clock signal, said source clock signal having m cycles for each cycle of said output clock signal and where m may be an odd or even integer number, said output clock signal having during each cycle a high interval and a low interval of equal duration, said divide-by-m counter comprising: clock source means for providing a non-inverted said source clock signal; modulo binary counter for counting up to a predetermined binary number and for providing a ripple carry pulse when reaching said predetermined binary number; counter preset means for presetting said modulo binary counter; counter clock selector means for providing a counter clock signal to increment said modulo binary counter including means for providing an inverted said source clock signal and when m is odd said counter clock selector means being selectively operable to provide for said high and low intervals of said output clock a different one of said inverted and non-inverted source clock signals to be said counter clock signal; and interval defining means for defining the beginning and ending of said high and low intervals based upon the occurrence of said ripple carry pulse.