US4912564A
Expired / Lapsed
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Clock signal generation apparatus
Assignee: Ricoh Printing Systems Ltd
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Filing: 1989-02-24
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Granted: 1990-03-27
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Expires: 2009-02-24
Abstract
Abstract A clock signal generation apparatus is disclosed in which an original signal source generates an original clock signal, a first frequency divider starts dividing the frequency of the original clock signal in response to the rise of the original clock signal and produces a frequency-divided clock signal, a second frequency divider starts dividing the frequency of the original clock signal in response to the fall of the original clock signal and produces a frequency-divided clock signal, a sync timing signal source generates a sync timing signal, and a selection circuit renders effective selected one of the first and second frequency dividers in accordance with a level of the original clock signal at selected one of the ride and fall timings of the sync timing signal thereby to produce the frequency-divided clock signal of the effective frequency divider as a clock signal.
Inventors
- 👤 Shouji Saitoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 00:47
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/04; H04N1/047; H04N1/053; H04N1/113; H04N1/1135; H04N1/12; H04N2201/00; H04N2201/024; H04N2201/02406; H04N2201/02439; H04N2201/04; H04N2201/047; H04N2201/04701; H04N2201/0471; H04N2201/04732; H04N2201/04744; H04N2201/04753; H04N2201/04758; H04N2201/04767; H04N2201/04781; H04N2201/04786; H04N2201/04794
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
136 words
A clock signal generation apparatus comprising: means for generating an original clock signal; first frequency-dividing means for starting the frequency division of said original clock signal in response to the rise of said original clock signal and producing a frequency-divided clock signal; second frequency-dividing means for starting the frequency division of said original clock signal in response to the fall of said original clock signal and producing a frequency-divided clock signal; means for generating a sync timing signal; and selection means for rendering one of said first and second frequency-dividing means effective selectively in accordance with a signal level of said original clock signal at selected one of the rise timing and fall timing of said sync timing signal, thereby producing a frequency-divided clock signal from the selected one of said first and second frequency-dividing means.
Claim 2
Dependent Claim
136 words
A clock signal generation apparatus comprising: means for generating an original clock signal; first frequency-dividing means for starting the frequency division of said original clock signal in response to the rise of said original clock signal and producing a frequency-divided clock signal; second frequency-dividing means for starting the frequency division of said original clock signal in response to the fall of said original clock signal and producing a frequency-divided clock signal; means for generating a sync timing signal; and selection means for rendering one of said first and second frequency-dividing means effective selectively in accordance with a signal level of said original clock signal at selected one of the rise timing and fall timing of said sync timing signal, thereby producing a frequency-divided clock signal from the selected one of said first and second frequency-dividing means.
Claim 3
Dependent Claim
79 words
A clock signal generation apparatus according to claim 1, wherein said selection means is a flip-flop circuit which holds one of said first and second frequency-dividing means effective selectively in accordance with the signal level of the original clock signal at the selected one of the rise and fall timings of said sync timing signal as long as said signal level at the selected one of the rise and fall timings of said sync timing signal remains the same.
Claim 4
Dependent Claim
40 words
A clock signal generation apparatus according to claim 2, wherein said flip-flop circuit is a D-type flip-flop circuit including a data input terminal supplied with said original clock signal and clock signal input terminal supplied with said sync timing signal.
Claim 5
Dependent Claim
61 words
A clock signal generation apparatus according to claim 1, wherein said first frequency-dividing means includes a first frequency divider, and said second frequency-dividing means includes an inverter connected to the output of said original clock signal generation means and a second frequency divider connected to the output of said inverter and having the same frequency-dividing rate as said first frequency divider.
Claim 6
Dependent Claim
144 words
A clock signal generation apparatus comprising: means for generating an original clock signal; first frequency-dividing means for starting the frequency division of said original clock signal in response to the rise of said original clock signal and producing a frequency-divided signal as a video clock signal; second frequency-dividing means for starting the frequency division of said original clock signal in response to the fall of said original clock signal and producing a frequency-divided signal as a video clock signal; means for generating a scanning sync timing signal; and selection means for rendering one of said first and second frequency-dividing means effective selectively in accordance with a signal level of said original clock signal at selected one of the rise timing and the fall timing of said sync timing signal, thereby producing an output signal of said selected frequency-divided signal as a video clock signal.
Claim 7
Dependent Claim
144 words
A clock signal generation apparatus comprising: means for generating an original clock signal; first frequency-dividing means for starting the frequency division of said original clock signal in response to the rise of said original clock signal and producing a frequency-divided signal as a video clock signal; second frequency-dividing means for starting the frequency division of said original clock signal in response to the fall of said original clock signal and producing a frequency-divided signal as a video clock signal; means for generating a scanning sync timing signal; and selection means for rendering one of said first and second frequency-dividing means effective selectively in accordance with a signal level of said original clock signal at selected one of the rise timing and the fall timing of said sync timing signal, thereby producing an output signal of said selected frequency-divided signal as a video clock signal.
Claim 8
Dependent Claim
45 words
A clock signal generation apparatus according to claim 5, wherein said scanning sync timing signal generation means includes a scanning beam detection circuit for detecting the passage of a scanning beam at a scanning start reference point to thereby produce said scanning sync timing signal.
Claim 9
Dependent Claim
80 words
A clock signal generation apparatus according to claim 5, wherein said selection means is a flip-flop circuit which holds one of said first and second frequency-dividing means selectively effective in accordance with the signal level of said original clock signal at selected one of the rise timing and the fall timing of said sync timing signal as long as said signal level at the selected one of the rise and fall timings of said sync timing signal remains the same.
Claim 10
Dependent Claim
40 words
A clock signal generation apparatus according to claim 7, wherein said flip-flop circuit is a D-type flip-flop including a data input terminal supplied with said original clock signal and a clock signal input terminal supplied with said sync timing signal.
Claim 11
Dependent Claim
61 words
A clock signal generation apparatus according to claim 5, wherein said first frequency-dividing means includes a first frequency divider, and said second frequency-dividing means includes an inverter connected to the output of said original clock signal generation means and a second frequency divider connected to the output of said inverter and having the same frequency-dividing rate as said first frequency divider.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-26 | 1993-09-25 | 1994-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-26 | 1997-09-25 | 1998-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-26 | 2001-09-25 | 2002-03-27 | $7700.00 | Window Closed / Lapsed |