Timer control with selectable frequency divider

Claim 1

A semiconductor integrated circuit for providing a drive signal output, said circuit comprising: a first input terminal for receiving an inputted clock signal; a frequency dividing circuit connected to said first input terminal for dividing the frequency of the inputted clock signal to provide a frequency-divided clock signal; a second input terminal for receiving an inputted horizontal synchronizing signal; a synchronizing circuit connected to said first and second input terminals for synchronizing the inputted clock signal and the inputted horizontal synchronizing signal to provide a clock-synchronized horizontal synchronizing signal; a selector circuit having (a) a first clock signal input connected to said frequency divider circuit for receipt of the frequency divided clock signal therefrom, (b) a first synchronizing signal input connected to said synchronizing circuit for receipt of the clock-synchronized horizontal synchronizing signal therefrom, (c) a second clock signal input connected to said first input terminal for receipt of the inputted clock signal therefrom, (d) a second synchronizing signal input connected to said second input terminal for receipt of the inputted horizontal synchronizing signal therefrom, (e) a clock signal output, and (f) a synchronizing signal output, said selector circuit in a first condition connecting said first clock signal input to said clock signal output, to provide as an output therefrom the frequency divided clock signal, and connecting said first synchronizing signal input to said synchronizing signal output, to provide as an output therefrom the clock-synchronized horizontal synchronizing signal, and in a second condition connecting said second clock signal input to said clock signal output, to provide as an output therefrom the inputted clock signal, and connecting said second synchronizing signal input to said synchronizing signal output, to provide as an output therefrom the inputted horizontal synchronizing signal; and a counter circuit having a count input connected to said selector circuit clock signal output for counting clock signals received therefrom, a clear input connected to said selector circuit synchronizing signal output for clearing the count of said counter circuit in response to the selector circuit synchronizing output, and an output for providing a count output; and an output control circuit connected to said counter circuit output for providing a control output signal on the basis of the count output, whereby in the selector circuit first condition the control output signal is based on the frequency divided clock signal and the clock-synchronized horizontal synchronizing signal, and in the selector circuit second condition the control output signal is based on the inputted clock signal and the inputted horizontal synchronizing signal.