US4066875A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed pulse counter
Assignee: Individual
•
Filing: 1976-09-17
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Granted: 1978-01-03
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Expires: 1996-09-17
Abstract
Abstract A high speed pulse counter suitable for mega-frequency pulse counting is disclosed with provision for auto-ranging between different gating time generators by means of a gating time selector actuated by an overflow pulse generated by the input pulse succeeding the display of a full register. A circuit divider provides for prescaling of the input signal applied to the register. The operation of the circuit divider is controlled by means for automatically controlling the divider circuit.
Inventors
- 👤 David R. Ollington
- 👤 Ishver L. Zala
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:53
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/40
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
250 words
A high speed pulse counter comprising an input for a pulse signal to be counted, a counter register, a counter display responsive to the pulse count of the register, a gate for gating the input signal to be counted, the gate being arranged between the input and the register, a plurality of different gating time generators arranged to be coupled in sequence each having a discrete gating time, a gating time selector adapted for stepping between and coupling a selected one of the gating time generators to the gate, the register generating an overflow pulse in response to receipt of that one of the input pulses of the input signal to be counted succeeding the input pulse which causes the counter display to indicate a full register within the time period of a currently operative gating time itself determined by the operative position of the gating time selector, the gating time selector being coupled to the register to receive any such overflow pulse and being operative to be stepped thereby to the next gating time generator in said sequence, at least one divider circuit adapted to sub-divide the input signal to be counted and arrange for only a predetermined ratio of said input pulses to be counted by the register, and means for automatically actuating the divider circuit comprising an input for the pulse signal to be counted to automatic control means operative to control a divider circuit selector switch according to whether said pulse signal exceeds a predetermined frequency.
Claim 2
Dependent Claim
250 words
A high speed pulse counter comprising an input for a pulse signal to be counted, a counter register, a counter display responsive to the pulse count of the register, a gate for gating the input signal to be counted, the gate being arranged between the input and the register, a plurality of different gating time generators arranged to be coupled in sequence each having a discrete gating time, a gating time selector adapted for stepping between and coupling a selected one of the gating time generators to the gate, the register generating an overflow pulse in response to receipt of that one of the input pulses of the input signal to be counted succeeding the input pulse which causes the counter display to indicate a full register within the time period of a currently operative gating time itself determined by the operative position of the gating time selector, the gating time selector being coupled to the register to receive any such overflow pulse and being operative to be stepped thereby to the next gating time generator in said sequence, at least one divider circuit adapted to sub-divide the input signal to be counted and arrange for only a predetermined ratio of said input pulses to be counted by the register, and means for automatically actuating the divider circuit comprising an input for the pulse signal to be counted to automatic control means operative to control a divider circuit selector switch according to whether said pulse signal exceeds a predetermined frequency.
Claim 3
Dependent Claim
254 words
A high speed pulse counter comprising an input for a pulse signal to be counted, a counter register, a counter display responsive to the pulse count of the register, a gate for gating the input signal to be counted, the gate being arranged between the input and the register, a plurality of different gating time generators arranged to be coupled in sequence each having a discrete gating time, a gating time selector adapted for stepping between and coupling a selected one of the gating time generators to the gate, the register generating an overflow pulse in response to receipt of that one of the input pulses of the input signal to be counted succeeding the input pulse which causes the counter display to indicate a full register within the time period of a currently operative gating time itself determined by the operative position of the gating time selector, the gating time selector being coupled to the register to receive any such overflow pulse and being operative to be stepped thereby to the next gating time generator in said sequence, at least one divider circuit adapted to sub-divide the input signal to be counted and arrange for only a predetermined ratio of said input pulses to be counted by the register, and means for automatically actuating the divider circuit comprising an input for the pulse signal to be counted to a frequency selector of automatic control means operative to control a divider circuit selector switch according to whether said pulse signal exceeds a predetermined frequency.
Claim 4
Dependent Claim
254 words
A high speed pulse counter comprising an input for a pulse signal to be counted, a counter register, a counter display responsive to the pulse count of the register, a gate for gating the input signal to be counted, the gate being arranged between the input and the register, a plurality of different gating time generators arranged to be coupled in sequence each having a discrete gating time, a gating time selector adapted for stepping between and coupling a selected one of the gating time generators to the gate, the register generating an overflow pulse in response to receipt of that one of the input pulses of the input signal to be counted succeeding the input pulse which causes the counter display to indicate a full register within the time period of a currently operative gating time itself determined by the operative position of the gating time selector, the gating time selector being coupled to the register to receive any such overflow pulse and being operative to be stepped thereby to the next gating time generator in said sequence, at least one divider circuit adapted to sub-divide the input signal to be counted and arrange for only a predetermined ratio of said input pulses to be counted by the register, and means for automatically actuating the divider circuit comprising an input for the pulse signal to be counted to a frequency selector of automatic control means operative to control a divider circuit selector switch according to whether said pulse signal exceeds a predetermined frequency.
Claim 5
Dependent Claim
16 words
A counter as defined in claim 2, wherein said frequency selector comprises a high pass filter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-02 | 1981-07-04 | 1982-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-02 | 1985-07-04 | 1986-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-02 | 1989-07-04 | 1990-01-03 | $7700.00 | Window Closed / Lapsed |