Circuit for dividing the frequency of a digital clock signal by two and one-half

Claim 2

A divide by two and one half (2.5) circuit for receiving a first clock signal and an asynchronous reset signal, said divide by two and one half (2.5) circuit arranged to transmit a second clock signal that has a period two and one half (2.5) times said first clock signal, said divide by two and one half (2.5) circuit comprising: clock selector means arranged to receive said first clock signal and to output a selected polarity of said first clock signal; ring counter means having a predetermined number of stages arranged to receive said clock selector means output, and to transmit an output signal that has a period of 3 times (3x) the signal received from said clock selector means; divide by two means arranged to receive said ring counter means output and to transmit an output signal that has a clock period of two times (2x) said ring counter means output signal, wherein said divide by two means output signal is input to said clock selector means and said ring counter means transmits said second clock signal; and reset synchronizer means arranged to initialize said ring counter means to a seed value other than all said stages at logic zero, in response to said asynchronous reset signal.

Claim 3

The divide by two and one half (2.5) circuit as claimed in claim 1, wherein: said reset synchronizer comprises a first and second D-FF each with a D input and an output, said first D-FF D input connected to said asynchronous reset signal, said second D-FF D input connected to said first D-FF output, said second D-FF output connected to said ring counter means, said first and second D-FF further including a common clock input connected to said clock selector means.

Claim 4

A divide by two and one half (2.5) circuit for receiving a first clock signal and an asynchronous reset signal, said divide by two and one half (2.5) circuit arranged to transmit a second clock signal that has a period two and one half (2.5) times said first clock signal, said divide by two and one half (2.5) circuit comprising: inverter means arranged to receive said first clock signal and transmit the complement polarity; clock selector means arranged to receive said first clock signal and said inverter means output, said clock selector means outputs a selected polarity of said first clock signal; ring counter means having a predetermined number of stages arranged to receive said clock selector means output, and to transmit an output signal that has a period of 3 times (3x) the signal received from said clock selector means; divide by two means arranged to receive said ring counter means output and to transmit an output signal that has a clock period of two times (2x) said ring counter means output signal, wherein said divide by two means output signal is input to said clock selector means and said ring counter means transmits said second clock signal; and reset synchronizer means arranged to initialize said ring counter means to a seed value other than all said stages at logic zero, in response to said asynchronous reset signal.

Claim 5

A divide by two and one half (2.5) circuit for receiving a first clock signal and an asynchronous reset signal, said divide by two and one half (2.5) circuit arranged to transmit a second clock signal that has a period two and one half (2.5) times said first clock signal, said divide by two and one half (2.5) circuit comprising: inverter means arranged to receive said first clock signal and transmit the complement polarity; clock selector means arranged to receive said first clock signal and said inverter means output, said clock selector means outputs a selected polarity of said first clock signal; ring counter means having a predetermined number of stages arranged to receive said clock selector means output, and to transmit an output signal that has a period of 3 times (3x) the signal received from said clock selector means; divide by two means arranged to receive said ring counter means output and to transmit an output signal that has a clock period of two times (2x) said ring counter means output signal, wherein said divide by two means output signal is input to said clock selector means and said ring counter means transmits said second clock signal; and reset synchronizer means arranged to initialize said ring counter means to a seed value other than all said stages at logic zero, in response to said asynchronous reset signal.

Claim 6

The divide by two and one half (2.5) circuit as claimed in claim 3, wherein: said reset synchronizer comprises a first and second D-FF each with a D input and an output, said first D-FF D input connected to said asynchronous reset signal, said second D-FF D input connected to said first D-FF output, said second D-FF output connected to said ring counter means, said first and second D-FF further including a common clock input connected to said clock selector means.

Claim 7

A divide by two and one half (2.5) circuit for receiving a first clock signal and an asynchronous reset signal, said divide by two and one half (2.5) circuit arranged to transmit a second clock signal that has a period two and one half (2.5) times said first clock signal, said divide by two and one half (2.5) circuit comprising: clock selector means arranged to receive said first clock signal and to output a selected polarity of said first clock signal; ring counter means arranged to receive said clock selector means output, and to transmit an output signal that has a period of 3 times (3x) the signal received from said clock selector means; divide by two means arranged to receive said ring counter means output and to transmit an output signal that has a clock period of two times (2x) said ring counter means output signal, wherein said divide by two means output signal is input to said clock selector means and said ring counter means transmits said second clock signal; and a first and second D-FF each with a D input and an output, said first D-FF D input connected to said asynchronous reset signal, said second F-FF D input connected to said first D-FF output, said second D-FF output connected to said ring counter means, said first and second D-FF further including a common clock input connected to said clock selector means.

Claim 8

A divide by two and one half (2.5) circuit for receiving a first clock signal and an asynchronous reset signal, said divide by two and one half (2.5) circuit arranged to transmit a second clock signal that has a period two and one half (2.5) times said first clock signal, said divide by two and one half (2.5) circuit comprising: clock selector means arranged to receive said first clock signal and to output a selected polarity of said first clock signal; ring counter means arranged to receive said clock selector means output, and to transmit an output signal that has a period of 3 times (3x) the signal received from said clock selector means; divide by two means arranged to receive said ring counter means output and to transmit an output signal that has a clock period of two times (2x) said ring counter means output signal, wherein said divide by two means output signal is input to said clock selector means and said ring counter means transmits said second clock signal; and a first and second D-FF each with a D input and an output, said first D-FF D input connected to said asynchronous reset signal, said second F-FF D input connected to said first D-FF output, said second D-FF output connected to said ring counter means, said first and second D-FF further including a common clock input connected to said clock selector means.