US3614632A
Expired / Lapsed
US
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Digital pulse width generator
Assignee: Individual
•
Filing: 1970-10-14
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Granted: 1971-10-19
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Expires: 1990-10-14
Abstract
Abstract Logic circuitry for generating a pulse of width n units of time where n is any positive integer.
Inventors
- 👤 Lawrence M Leibowitz
- 👤 Richard K Baldauf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 02:26
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/78; H03M; H03M1/00; H03M1/66; H03M1/82
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
86 words
A pulse generator comprising: a source of clock pulses; a counter coupled to said source; a register comprising a plurality of flip-flops coupled to said counter and said source; switching means coupled to said register for storing a number in said register; and logic means coupled between said counter and said register for resetting said register upon said counter reaching the number stored in said register; said register supplying a pulse having a width proportional to said stored number upon being reset by said logic means.
Claim 2
Dependent Claim
86 words
A pulse generator comprising: a source of clock pulses; a counter coupled to said source; a register comprising a plurality of flip-flops coupled to said counter and said source; switching means coupled to said register for storing a number in said register; and logic means coupled between said counter and said register for resetting said register upon said counter reaching the number stored in said register; said register supplying a pulse having a width proportional to said stored number upon being reset by said logic means.
Claim 3
Dependent Claim
55 words
A pulse generator as recited in claim 1 wherein said switching means comprises a plurality of switches, one switch coupled to a respective flip-flop; and a first NAND gate coupled to one output of all of said flip-flops; whereby said first NAND gate output supplies said pulse upon the setting of any of said switches.
Claim 4
Dependent Claim
50 words
A pulse generator is recited in claim 2 wherein said logic means comprises a plurality of NAND gates; wherein said register is coupled to said counter via said first NAND gate and a second NAND gate; and wherein said source is coupled to said counter via said second NAND gate.
Claim 5
Dependent Claim
31 words
A pulse generator as recited in claim 3 including: a gate coupled between each of said switches and its respective flip-flop, said one output from said flip-flops coupled to said gate.
References Cited (Backward Citations)
US3002151A
Cited
US3539926A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-18 | 1975-04-19 | 1975-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-18 | 1979-04-19 | 1979-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-18 | 1983-04-19 | 1983-10-19 | $7700.00 | Window Closed / Lapsed |