US4348640A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Divide by three clock divider with symmertical output
Assignee: Boeing North American Inc
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Filing: 1980-09-25
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Granted: 1982-09-07
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Expires: 2000-09-25
Abstract
Abstract A digital circuit receives symmetrical clock pulses of frequency F and outputs symmetrical pulses of frequency 1/3 F. A divide by one and one-half circuit clocks a divide by two flip-flop resulting in a symmetrical divide by three output. The divide by one and one-half circuit includes a pair of JK flip-flops and logic gates which receive clock pulses of frequency F and generate a plurality of staggered signal streams with nonsymmetrical pulses of frequency 1/3 F and a duty cycle of substantially 33%. The input clock pulses are gated against two of these streams to provide an output pulse during the first half of the duty portion of a cycle of one of the streams, and another output pulse during the second half of the duty portion of a cycle of the other stream, to provide an output frequency of 2/3 F which then clocks the divide by two flip-flop.
Inventors
- 👤 Steven J. Clendening
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:37
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/08; H03K23/00; H03K23/40; H03K23/50; H03K23/502; H03K23/505
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
74 words
A divide by three digital clock divider circuit providing a symmetrical output, comprising: a divide by one and one-half circuit comprising flip-flop means and gate means for receiving clock pulses of frequency F and generating nonsymmetrical pulses of frequency 1/3F, and for gating said clock pulses with said nonsymmetrical pulses and generating pulses of frequency 2/3F; and divide by two means receiving said pulses of frequency 2/3F and outputting symmetrical pulses of frequency 1/3F.
Claim 2
Dependent Claim
74 words
A divide by three digital clock divider circuit providing a symmetrical output, comprising: a divide by one and one-half circuit comprising flip-flop means and gate means for receiving clock pulses of frequency F and generating nonsymmetrical pulses of frequency 1/3F, and for gating said clock pulses with said nonsymmetrical pulses and generating pulses of frequency 2/3F; and divide by two means receiving said pulses of frequency 2/3F and outputting symmetrical pulses of frequency 1/3F.
Claim 3
Dependent Claim
59 words
The invention according to claim 1 wherein said divide by two means comprises a divide by two flip-flop clocked by said 2/3F pulses from said divide by one and one-half circuit, said flip-flop having an opposite polarity output returned to an input to be clocked therethrough by said 2/3F pulses to provide symmetrical 1/3F pulses on another output thereof.
Claim 4
Dependent Claim
41 words
The invention according to claim 1 wherein said divide by one and one-half circuit generates a plurality of nonaligned staggered signal streams with nonsymmetrical pulses of frequency 1/3F, and said gate means gates said clock pulses against two of said streams.
Claim 5
Dependent Claim
122 words
The invention according to claim 3 wherein: a first said 1/3F stream has a duty cycle of substantially 33% and is gated against said clock pulses to yield output pulses during the first half of the duty portion of a cycle of said first 1/3F stream. a second said 1/3F stream has a duty cycle of substantially 33% immediately following the duty portion of said first 1/3F stream, said second 1/3F stream being gated against said clock pulses to yield output pulses during the second half of the duty portion of a cycle of said second 1/3F stream, such that the output of said divide by one and one-half circuit provides pulses of frequency 2/3F with a duty cycle of substantially 33%.
Claim 6
Dependent Claim
101 words
The invention according to claim 4 wherein said divide by one and one-half circuit comprises: a first flip-flop clocked by said clock pulses; a second flip-flop clocked by said clock pulses and having an input connected to an output of said first flip-flop; means connecting an output of said second flip-flop to an input of said first flip-flop; gate means receiving said clock pulses and receiving outputs of said first and second flip-flops, and including a pair of gates output in parallel to a common connection to said divide by two means, each gate providing alternate pulses in said 2/3F signal.
Claim 7
Dependent Claim
102 words
The invention according to claim 5 wherein said gate means comprises: a first gate having a first input connected to an output of said first flip-flop, and a second input connected to an output of said second flip-flop; means providing inverted clock pulses; a second gate having a first input connected to the output of said first gate, and having a second input receiving inverted clock pulses; and a third gate having a first input connected to an output of said second flip-flop, and having a second input receiving noninverted clock pulses, said second and third gates forming said pair of gates.
Claim 8
Dependent Claim
70 words
The invention according to claim 6 wherein: said first and second flip-flops comprise JK flip-flops, the Q output of the first JK flip-flop connected to the J input of the second JK flip-flop, the Q output of said second JK flip-flop connected to the J input of said first JK flip-flop; said first gate comprises a NOR gate input from the Q outputs of said first and second JK flip-flops;
Claim 9
Dependent Claim
35 words
said second and thrid gates comprise AND gates, one of which is input from said Q output of said second JK flip-flop, the other of which is input from the output of said NOR gate.
Claim 10
Dependent Claim
35 words
said second and thrid gates comprise AND gates, one of which is input from said Q output of said second JK flip-flop, the other of which is input from the output of said NOR gate.
Claim 11
Dependent Claim
169 words
A divide by three digital clock divider circuit providing a symmetrical output, comprising: a divide by one and one-half circuit comprising flip-flop means and gate means for receiving clock pulses of frequency F and generating a plurality of nonaligned staggered signal streams with nonsymmetrical pulses of frequency 1/3F including first and second 1/3F streams each having a duty cycle of substantially 33%, said gate means gating said clock pulses against said first 1/3F stream to yield output pulses during the first half of the duty portion of a cycle of said first 1/3F stream, and gating said clock pulses against said second 1/3F stream to yield output pulses during the second half of the duty portion of a cycle of said second 1/3F stream, such that the output of said divide by one and one-half circuit provides pulses of frequency 2/3F with a duty cycle of substantially 33%; and a divide by two flip-flop clocked by said divide by one and one-half circuit to provide symmetrical 1/3F output pulses.
Claim 12
Dependent Claim
169 words
A divide by three digital clock divider circuit providing a symmetrical output, comprising: a divide by one and one-half circuit comprising flip-flop means and gate means for receiving clock pulses of frequency F and generating a plurality of nonaligned staggered signal streams with nonsymmetrical pulses of frequency 1/3F including first and second 1/3F streams each having a duty cycle of substantially 33%, said gate means gating said clock pulses against said first 1/3F stream to yield output pulses during the first half of the duty portion of a cycle of said first 1/3F stream, and gating said clock pulses against said second 1/3F stream to yield output pulses during the second half of the duty portion of a cycle of said second 1/3F stream, such that the output of said divide by one and one-half circuit provides pulses of frequency 2/3F with a duty cycle of substantially 33%; and a divide by two flip-flop clocked by said divide by one and one-half circuit to provide symmetrical 1/3F output pulses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-09-06 | 1986-03-08 | 1986-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-09-06 | 1990-03-08 | 1990-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-09-06 | 1994-03-08 | 1994-09-07 | $7700.00 | Window Closed / Lapsed |