US3902125A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Symmetric output, digital by three counter
Assignee: United States Department of the Army
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Filing: 1974-06-18
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Granted: 1975-08-26
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Expires: 1994-06-18
Abstract
Abstract A digital divide by three ( divided by 3) counter providing a symmetrical square wave output waveform from a square wave input signal utilizing digital logic devices. The circuitry includes a conventional divide by three digital counter whose nonsymmetrical square wave output is fed to one input of an AND gate and to one input of a delay type flip-flop circuit after being fed through a logic inverter. The square wave input fed to the counter is additionally fed to the other input of the AND gate and the delay type flip-flop, whereupon the output of the AND gate and flip-flop are fed to an OR gate whose output comprises the desired symmetrical waveform.
Inventors
- 👤 Jr George R Oliva
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:14
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/08; H03K23/00; H03K23/40; H03K23/50; H03K23/502; H03K23/505
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
231 words
A digital divide by three counter circuit providing a symmetrical output, comprising in combination: input means adapted to receive a binary input signal; a divide by three counter circuit coupled to said input means, being operable to provide a first binary divide by three output signal; a first logic circuit comprising a coincidence logic gate having two inputs respectively coupled to said input means and to said counter circuit and being responsive to said binary input signal and said first binary divide by three output signal to provide a first intermediate output signal comprising one and a half cycles of said input signal; a logic inverter circuit coupled to said counter circuit for providing a complementary first binary divide by three output signal; a bistable device having one input coupled to said input means and another input to the output of said logic inverter circuit, being responsive to said input signal and said complementary first divide by three output signal to provide a second intermediate output signal comprising a time delay version of said complementary first divide by three output signal; and a second logic circuit comprising a noncoincidence logic gate having two inputs respectively coupled to said bistable device and said first logic circuit and being responsive to said first and second intermediate output signals to provide a composite output signal which is a symmetrical divide by three output signal.
Claim 2
Dependent Claim
231 words
A digital divide by three counter circuit providing a symmetrical output, comprising in combination: input means adapted to receive a binary input signal; a divide by three counter circuit coupled to said input means, being operable to provide a first binary divide by three output signal; a first logic circuit comprising a coincidence logic gate having two inputs respectively coupled to said input means and to said counter circuit and being responsive to said binary input signal and said first binary divide by three output signal to provide a first intermediate output signal comprising one and a half cycles of said input signal; a logic inverter circuit coupled to said counter circuit for providing a complementary first binary divide by three output signal; a bistable device having one input coupled to said input means and another input to the output of said logic inverter circuit, being responsive to said input signal and said complementary first divide by three output signal to provide a second intermediate output signal comprising a time delay version of said complementary first divide by three output signal; and a second logic circuit comprising a noncoincidence logic gate having two inputs respectively coupled to said bistable device and said first logic circuit and being responsive to said first and second intermediate output signals to provide a composite output signal which is a symmetrical divide by three output signal.
Claim 3
Dependent Claim
16 words
The counter circuit as defined by claim 1 wherein said bistable device comprises a flip-flop circuit.
Claim 4
Dependent Claim
17 words
The counter circuit as defined by claim 2 wherein said flip-flop circuit comprises a delay type flip-flop.
Claim 5
Dependent Claim
34 words
The counter circuit as defined by claim 1 wherein said coincidence logic gate comprises an AND gate, said non-coincidence logic Gate comprises an OR gate and said logic inverter circuit comprises a NOT gate.
Claim 6
Dependent Claim
78 words
The counter circuit as defined by claim 1 wherein said bistable device comprises a delay type flip-flop circuit having independent data, set, reset, and clock inputs and Q and Q outputs, and additionally including circuit means connecting said set and reset inputs to a point of reference potential, said data input to said output of said logic inverter circuit, said clock input to said input means, and said Q output to one input of said second logic circuit.
Claim 7
Dependent Claim
23 words
The counter circuit as defined by claim 1 wherein said divide by three counter circuit comprises a first and second interconnected flip-flop circuit.
Claim 8
Dependent Claim
24 words
The counter circuit as defined by claim 6 wherein said first and second interconnected flip-flop circuits comprises first and second delay type flip-flop circuits.
Claim 9
Dependent Claim
140 words
The counter circuit as defined by claim 7 wherein each said first and second delay type flip-flop circuit has independent data, set, reset, and clock inputs and Q and Q outputs, and additionally including circuit means connecting the reset and data inputs of the first flip-flop and the set and reset inputs of the second flip-flop to a point of reference potential, circuit means commonly coupling said input means to the clock input of both flip-flops, circuit means respectively interconnecting the Q output of said first flip-flop to the data input of said second flip-flop and said Q output of said second flip-flop back to the set input of said first flip-flop, and circuit means commonly connecting the Q output of said second flip-flop to one input of said first logic circuit and to the input of said logic inverter.
Claim 10
Dependent Claim
79 words
The counter circuit as defined by claim 8 and wherein said bistable device comprises a delay type flip-flop circuit having independent data, set, reset, and clock inputs and Q and Q outputs, and additionally including circuit means connecting said set and reset inputs to a point of reference potential, said data input to said output of said logic inverter circuit, said clock input to said input means, and said Q output to one input of said second logic circuit.
Claim 11
Dependent Claim
34 words
The counter circuit as defined by claim 9 wherein said first logic circuit comprises an AND gate, said second logic circuit comprises an OR gate, and said logic inverter circuit comprises a NOT gate.
References Cited (Backward Citations)
US3439278A
Cited
US3571727A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-25 | 1979-02-24 | 1979-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-25 | 1983-02-24 | 1983-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-25 | 1987-02-24 | 1987-08-26 | $7700.00 | Window Closed / Lapsed |