US3943379A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Symmetrical odd modulus frequency divider
Assignee: RCA Corp
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Filing: 1974-10-29
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Granted: 1976-03-09
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Expires: 1994-10-29
Abstract
Abstract Logic circuit for dividing an input frequency symmetrically by an odd number without producing spurious transients.
Inventors
- 👤 William George McGuffin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 08:32
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/54; H03K23/544; H03K21/00; H03K21/08
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
156 words
A circuit for symmetrically dividing by an odd modulus m comprising n flip-flop means for storing signals, where n = (m+3)/2; a source of input pulses to be divided; complementing means for complementing said input pulses; first coupling means for controlling the first (n - 1) flip-flop means with said input pulses; second coupling means for controlling the nth flip-flop means with said complemented input pulses; means for coupling the signal stored in the i-th flip-flop means to the j-th flip-flop means for storage, where i = 1, 2, . . . , n-1 and j = 2, 3, . . . , n; first gating means responsive to the signals stored in the (n-1)th and (n-2)th flip-flop means for producing a signal which is stored in the first flip-flop means by each input pulse; and second gating means responsive to the signals stored in the nth and (n-1)th flip-flop means for producing an output signal.
Claim 2
Dependent Claim
156 words
A circuit for symmetrically dividing by an odd modulus m comprising n flip-flop means for storing signals, where n = (m+3)/2; a source of input pulses to be divided; complementing means for complementing said input pulses; first coupling means for controlling the first (n - 1) flip-flop means with said input pulses; second coupling means for controlling the nth flip-flop means with said complemented input pulses; means for coupling the signal stored in the i-th flip-flop means to the j-th flip-flop means for storage, where i = 1, 2, . . . , n-1 and j = 2, 3, . . . , n; first gating means responsive to the signals stored in the (n-1)th and (n-2)th flip-flop means for producing a signal which is stored in the first flip-flop means by each input pulse; and second gating means responsive to the signals stored in the nth and (n-1)th flip-flop means for producing an output signal.
Claim 3
Dependent Claim
183 words
A logic circuit for symmetrically dividing an input signal by three comprising the combination: source of input signals to be divided; first and second flip-flop means responsive to the input signals for storing a signal between input signals equivalent to the value of an applied second signal at the leading edge of the input signal; third flip-flop means responsive to a 180° phase shift of the input signal for storing a signal between shifted input signals equivalent to the value of an applied second signal at the leading edge of the shifted input signal; means for coupling the stored signal in said first flip-flop means as the applied second signal to said second flip-flop means; means for coupling the stored signal in said second flip-flop means as the applied second signal to said third flip-flop means; first gating means responsive to the stored signals of said first and second flip-flop means for providing an applied second signal to said first flip-flop means; and second gating means responsive to the signals stored in said second and third flip-flop means for producing an output signal.
Claim 4
Dependent Claim
183 words
A logic circuit for symmetrically dividing an input signal by three comprising the combination: source of input signals to be divided; first and second flip-flop means responsive to the input signals for storing a signal between input signals equivalent to the value of an applied second signal at the leading edge of the input signal; third flip-flop means responsive to a 180° phase shift of the input signal for storing a signal between shifted input signals equivalent to the value of an applied second signal at the leading edge of the shifted input signal; means for coupling the stored signal in said first flip-flop means as the applied second signal to said second flip-flop means; means for coupling the stored signal in said second flip-flop means as the applied second signal to said third flip-flop means; first gating means responsive to the stored signals of said first and second flip-flop means for providing an applied second signal to said first flip-flop means; and second gating means responsive to the signals stored in said second and third flip-flop means for producing an output signal.
Claim 5
Dependent Claim
16 words
The invention as claimed in claim 2 wherein said first gating means is a NAND gate.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-03-09 | 1979-09-08 | 1980-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-03-09 | 1983-09-08 | 1984-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-03-09 | 1987-09-08 | 1988-03-09 | $7700.00 | Window Closed / Lapsed |