US3851258A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gateless logic for producing selectable phase clock pulses
Assignee: RCA Corp
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Filing: 1973-12-13
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Granted: 1974-11-26
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Expires: 1993-12-13
Abstract
Abstract Circuit for dividing an input frequency by two having an output signal phase controlled by a signal indicating a 0* or 180* phase shift.
Inventors
- 👤 D Freedman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:26
CPC Classifications
H; H03; H03K; H03K21/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
127 words
The combination comprising: input means for pulses to be divided; first flip-flop means coupled to said input means for producing true and complement signals that change state in response to each input pulse; control means for producing true and complement control signals in response to a signal indicating selected phase; second and third flip-flop means coupled to be responsive to said input pulses, to the output signals of said first flipflop means, and to said control signals for producing an output signal in response to a pulse depending on the states of the control signals and said first flip-flop means; and fourth flip-flop means coupled to the input pulse means for producing an output signal in response to the states of said second and third flip-flop means.
Claim 2
Dependent Claim
127 words
The combination comprising: input means for pulses to be divided; first flip-flop means coupled to said input means for producing true and complement signals that change state in response to each input pulse; control means for producing true and complement control signals in response to a signal indicating selected phase; second and third flip-flop means coupled to be responsive to said input pulses, to the output signals of said first flipflop means, and to said control signals for producing an output signal in response to a pulse depending on the states of the control signals and said first flip-flop means; and fourth flip-flop means coupled to the input pulse means for producing an output signal in response to the states of said second and third flip-flop means.
Claim 3
Dependent Claim
48 words
The invention as claimed in claim 1 wherein said second flip-flop is responsive to the true signals from both said control means and said first flip-flop means and the third flip-flop means is responsive to the complemented signals from both said control means and said first flip-flop means.
Claim 4
Dependent Claim
56 words
The invention as claimed in claim 1 wherein said second flip-flop is responsive to the true signal from said control means and to the complement signals from said first flip-flop means and the third flip-flop means is responsive to the complement signal from said control means and to the true signal from said first flip-flop means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-25 | 1978-05-27 | 1978-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-25 | 1982-05-27 | 1982-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-25 | 1986-05-27 | 1986-11-26 | $7700.00 | Window Closed / Lapsed |