Timing current supply for a system of two channel circuits

Claim 1

A timing current supply for a system of two-channel circuits, which provides binary in-phase and anti-phase variables in the form of two rectangular signal voltages of equal given repetition frequency and amplitude and a phase difference of 180* for differentiating between the two values, control pulses of at least twice the given repetition frequency and positioned outside of the edge ranges of the rectangular pulses of the signal voltages, and control circuits which process the control pulses only during existing an anti-phase relationship of the signal voltages, comprising: a control pulse generator operable to produce a symmetric rectangular voltage as phase control pulses, to produce the control pulses starting at the edges of said phase control pulses, and to produce edge control pulses each positioned between the control pulses; two first D flip-flops each having a trigger input, an output and a conditional input connected to said pulse generator to receive said phase control pulses; two second D flip-flops each having a trigger input, an output, and a conditional input connected to respective ones of said outputs of said two first D flip-flops and which are operable to provide said in-phase and anti-phase signals at their outputs; a control circuit having two inputs connected to respective outputs of said two second D flip-flops, an input connected to said pulse generator to receive said control pulses and an output connected to said trigger input of one of said two first D flip-flops, said control circuit operable to pass said control pulses in response to receipt of anti-phase signals from said second D flip-flops; a switching mechanism having inputs connected to respective ones of said outputs of said two second D flip-flops and to said control circuit and an output connected to said trigger input of the other of said two first D flip-flops, and operable in response to an anti-phase relationship of the signals at its input to supply said control pulses from said control circuit to said other D flip-flops as trigger pulses; a set-reset flip-flop having a first input connected to the output of said control circuit, a second input connected to said pulse generator to receive said edge control pulses and an output connected to said trigger inputs of said second D flip-flops for triggering said second D flip-flops to receive data from the outputs of said first D flip-flops.