Method and apparatus for multi-level input voltage receiver circuit

Claim 2

A receiver circuit, comprising: first stage circuitry for receiving an input signal, wherein the first stage circuitry includes: a first stage output node, first pullup circuitry coupled to an input node and the first stage output node for driving a voltage on the first stage output node in response to the input signal, and circuitry for overvoltage protection coupled to the input node; and second stage circuitry coupled to the first stage output node, wherein the second stage circuitry includes: second pullup circuitry coupled to the first stage output node for driving the voltage on the first stage output node in response to the input signal, and circuitry for disabling the second pullup circuitry when the receiver is used in a high voltage input signal mode, so that the second pullup circuitry, when disabled, will not oppose the input signal driving the first stage output node voltage downward.

Claim 3

The receiver of claim 1, wherein the overvoltage protection circuitry includes a pass gate.

Claim 4

The receiver of claim 2, wherein the first pullup circuitry includes a transistor having a modulating electrode operably connected to the input node, one conducting electrode connected to the voltage supply and another conducting electrode connected to the first stage output node.

Claim 5

A receiver, comprising; first circuitry, including: a pass gate having a first and second conducting electrode, the first conducting electrode being coupled to an input node for receiving an input signal and protecting against overvoltage of the signal, and a first pullup transistor having a modulating electrode and a first and second conducting electrode, the modulating electrode being coupled to the input node for receiving the input signal, one of the first pullup transistor conducting electrodes being connected at a first stage output node to the pass gate second conducting electrode, and the other of the first pullup transistor conducting electrodes being for operable connection to a voltage supply; and second circuitry, including; a number of inverters operably connected in series, wherein the first inverter in the series has an input operably connected to the first stage output node, a second pullup transistor having a modulating electrode and a first and second conducting electrode, the modulating electrode being operably connected to an output node of the first inverter, one of the conducting electrodes being operably connected to the first stage output node, and the other of the electrodes being for operable connection to the voltage supply, and a disabling transistor having a modulating electrode and a first and second conducting electrode, the disabling transistor modulating electrode being for receiving a control signal, and the disabling transistor conducting electrodes being interposed between the second pullup transistor and the first stage output node.

Claim 6

A receiver, comprising; first circuitry, including: a pass gate having a first and second conducting electrode, the first conducting electrode being coupled to an input node for receiving an input signal and protecting against overvoltage of the signal, and a first pullup transistor having a modulating electrode and a first and second conducting electrode, the modulating electrode being coupled to the input node for receiving the input signal, one of the first pullup transistor conducting electrodes being connected at a first stage output node to the pass gate second conducting electrode, and the other of the first pullup transistor conducting electrodes being for operable connection to a voltage supply; and second circuitry, including; a number of inverters operably connected in series, wherein the first inverter in the series has an input operably connected to the first stage output node, a second pullup transistor having a modulating electrode and a first and second conducting electrode, the modulating electrode being operably connected to an output node of the first inverter, one of the conducting electrodes being operably connected to the first stage output node, and the other of the electrodes being for operable connection to the voltage supply, and a disabling transistor having a modulating electrode and a first and second conducting electrode, the disabling transistor modulating electrode being for receiving a control signal, and the disabling transistor conducting electrodes being interposed between the second pullup transistor and the first stage output node.

Claim 7

In a receiver circuit having i) first stage circuitry, including a first stage output node, first pullup circuitry and circuitry for overvoltage protection, and ii) second stage circuitry, operably connected to the first stage output node, including second pullup circuitry, a method comprising the steps of: disabling the second pullup circuitry when the receiver is used in a high voltage input signal mode; enabling the second pullup circuitry when receiver is used in a low voltage input signal mode; receiving the input signal by the first stage circuitry; driving the first stage output node upward toward essentially a voltage supply level by the first pullup circuitry in response to the input signal rising when the second pullup circuitry is disabled, wherein the first stage output node voltage is allowed to fall in response to the input signal falling, and the second pullup circuitry, being disabled, does not oppose the first stage output node voltage falling; and driving the first stage output node toward essentially the voltage supply level using the first and second pullup circuitry, in response to the input signal rising when the second pullup circuitry is enabled.

Claim 8

In a receiver circuit having i) first stage circuitry, including a first stage output node, first pullup circuitry and circuitry for overvoltage protection, and ii) second stage circuitry, operably connected to the first stage output node, including second pullup circuitry, a method comprising the steps of: disabling the second pullup circuitry when the receiver is used in a high voltage input signal mode; enabling the second pullup circuitry when receiver is used in a low voltage input signal mode; receiving the input signal by the first stage circuitry; driving the first stage output node upward toward essentially a voltage supply level by the first pullup circuitry in response to the input signal rising when the second pullup circuitry is disabled, wherein the first stage output node voltage is allowed to fall in response to the input signal falling, and the second pullup circuitry, being disabled, does not oppose the first stage output node voltage falling; and driving the first stage output node toward essentially the voltage supply level using the first and second pullup circuitry, in response to the input signal rising when the second pullup circuitry is enabled.