US5378945A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage level converting buffer circuit
Assignee: Hewlett Packard Development Co LP
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Filing: 1993-07-26
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Granted: 1995-01-03
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Expires: 2013-07-26
Abstract
Abstract A voltage level conversion buffer circuit including a first and a second transistor each having a gate, a drain, and a source. The drain of the first transistor and the gate of the second transistor are connected together to provide an input to the buffer circuit, and the gate of the first transistor and the drain of the second transistor are connected to a supply voltage. The sources of the first and second transistors are connected together to provide an output for the buffer circuit.
Inventors
- 👤 Hamid Partovi
- 👤 Steven W. Butler
- 👤 Laun Q. Tran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:29
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00315; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
87 words
A voltage level conversion buffer circuit having an input and an output, comprising: a first transistor including a gate, a drain, and a source, said gate is connected to a supply voltage; and a second transistor including a gate, a drain, and a source, said drain of said second transistor is connected to said supply voltage, said gate of said second transistor is connected to said drain of said first transistor, and said source of said second transistor is connected to said source of said first transistor.
Claim 2
Dependent Claim
87 words
A voltage level conversion buffer circuit having an input and an output, comprising: a first transistor including a gate, a drain, and a source, said gate is connected to a supply voltage; and a second transistor including a gate, a drain, and a source, said drain of said second transistor is connected to said supply voltage, said gate of said second transistor is connected to said drain of said first transistor, and said source of said second transistor is connected to said source of said first transistor.
Claim 3
Dependent Claim
30 words
The buffer circuit according to claim 1, wherein said buffer circuit has the input connected to the drain of said first transistor and to the gate of said second transistor.
Claim 4
Dependent Claim
39 words
The buffer circuit according to claim 1, further comprising: an integrated circuit logic element, with the source of said first transistor and the source of said second transistor being connected to an input of said integrated circuit logic element.
Claim 5
Dependent Claim
16 words
The buffer circuit according to claim 3, wherein said integrated circuit logic element is an inverter.
Claim 6
Dependent Claim
24 words
The buffer circuit according to claim 3, wherein said first transistor, said second transistor, and said logic element are part of a logic component.
Claim 7
Dependent Claim
14 words
The buffer circuit according to claim 5, wherein said component uses said supply voltage.
Claim 8
Dependent Claim
19 words
The buffer circuit according to claim 1, wherein said first and said second transistors are N-channel metal-oxide-semiconductor field-effect transistors.
Claim 9
Dependent Claim
40 words
The buffer circuit according to claim 2, further comprising: a driving component connected to said input terminal, with said driving component being capable of providing a signal to said input terminal having a voltage level greater than said supply voltage.
Claim 10
Dependent Claim
156 words
In combination: a driving component using a first voltage supply Vdd; a voltage level conversion buffer circuit comprising: a first transistor including a gate, a drain, and a source; and a second transistor including a gate, a drain, and a source, said gate of said second transistor is connected to said drain of said first transistor to provide an input of said buffer circuit, and said source of said second transistor is connected to said source of said first transistor to provide an output of said buffer circuit, and wherein said input of said buffer circuit is coupled to said driving component; and a logic element including an input coupled to said output of said buffer circuit, and wherein said logic element uses a second supply voltage which is less than said first supply voltage and said gate of said first transistor and said drain of said second transistor are coupled to said second supply voltage.
Claim 11
Dependent Claim
156 words
In combination: a driving component using a first voltage supply Vdd; a voltage level conversion buffer circuit comprising: a first transistor including a gate, a drain, and a source; and a second transistor including a gate, a drain, and a source, said gate of said second transistor is connected to said drain of said first transistor to provide an input of said buffer circuit, and said source of said second transistor is connected to said source of said first transistor to provide an output of said buffer circuit, and wherein said input of said buffer circuit is coupled to said driving component; and a logic element including an input coupled to said output of said buffer circuit, and wherein said logic element uses a second supply voltage which is less than said first supply voltage and said gate of said first transistor and said drain of said second transistor are coupled to said second supply voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-02 | 1998-07-04 | 1999-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-02 | 2002-07-04 | 2003-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-02 | 2006-07-04 | 2007-01-03 | $7700.00 | Window Closed / Lapsed |