High speed CMOS transition detector circuit

Claim 2

A circuit for detecting transitions in voltage, the circuit comprising: at least one input having a first signal corresponding to said transitions in voltage; at least one inverted input having a second signal corresponding to inversions of said transitions in voltage; a supply voltage and a reference potential; an output for providing an output voltage upon detection of one of said transitions or of said inversions; a P-channel transistor having a source-drain path and having a gate, said source-drain path of said P-channel transistor connected between said supply voltage and said output, said gate of said P-channnel transistor connected to said reference potential; a first and second N-channel transistors, each having a source-drain path and having a gate, said source-drain paths of said first and second N-channel transistors connected in series between said output and said reference potential; first and second N-channel leaker devices, each having a source-drain path and having a gate, said source-drain path of said first N-channel leaker device connected between a said inverted input and said gate of said first N-channel transistor, said gate of said first N-channel leaker device connected to said supply voltage, said source-drain path of said second N-channel leaker device connected between a said input and said gate of said second N-channel transistor, said gate of said second N-channel leaker device connected to said supply voltage.

Claim 3

The circuit of claim 1, including a first risetime control device having a source-drain path and having a gate, said source-drain path of said first risetime control device connected between said supply voltage and said gate of said first N-channel transistor, said gate of said first risetime control device connected to a said input; and a second risetime control device having a source-drain path and having a gate, said source-drain path of said second risetime control device connected between said supply voltage and said gate of said second N-channel transistor, said gate of said second risetime control device connected to a said inverted input.

Claim 4

The circuit of claim 1, including a first risetime control transistor of a predetermined conductivity-type having a source-drain path and having a gate, said source-drain path of said first risetime control transistor connected between said supply voltage and said gate of said first N-channel transistor, said gate of said fist risetime control transistor connected to a said input; and a second risetime control transistor of said predetermined conductivity-type having a source-drain path and having a gate, said source-drain path of said second risetime control transistor connected between said supply voltage and said gate of said second N-channel transistor, said gate of said second risetime control transistor connected to a said inverted input; wherein said predetermined conductivity-type is P-type.

Claim 5

The circuit of claim 1, including a first risetime control transistor having a source-drain channel path and having a gate, said source-drain channel path of said first risetime control transistor having a predetermined width and length, said source-drain channel path of said first risetime control transistor connected between said supply voltage and said gate of said first N-channel transistor, said gate of said first risetime control transistor connected to a said input; and a second risetime control transistor having a source-drain channel path and having a gate, said source-drain channel path of said second risetime control transistor having a predetermined width and length, said source-drain channel path of said second risetime control transistor connected between said supply voltage and said gate of said second N-channel transistor, said gate of said second risetime control transistor connected to a said inverted input; wherein said risetime of said output voltage at said output is determined by said predetermined source-drain channel widths and lengths of said first and second risetime control devices.

Claim 6

The circuit of claim 1, wherein said first and second leaker devices are N-channel field-effect transistors.

Claim 7

The circuit of claim 1, wherein the duration of said output voltage at said output is determined by the widths and lengths of said source-drain paths of said first and second leaker devices.

Claim 8

The circuit of claim 1, including an inverter having an input, said input of said inverter connected to said output of said circuit.

Claim 9

The circuit of claim 1, including an inverter having an input and having an output, said input of said inverter connected to said output of said circuit; and a NOR circuit having an input, said input of said NOR circuit connected to said output of said inverter.

Claim 10

The circuit of claim 1, including an inverter having an input and having an output, said input of said inverter connected to said output of said circuit; a NOR circuit having an input and having an output, said input of said NOR circuit connected to said output of said inverter; and a NAND circuit having an input, said input of said NAND circuit connected to said output of said NOR circuit.

Claim 11

A circuit for detecting transitions in voltage at a terminal of an integrate logic array, the circuit comprising: a supply voltage; a reference potential; at least one input having a signal corresponding to said transitions in voltage; at least one inverted input having a second signal corresponding to inversions of said transitions in voltage; an output for providing an output voltage upon detection of one of a said transition of said inversions; a P-channel transistor having a source-drain path and having a gate, said source-drain path of said P-channel transistor connected between said supply voltage and said output, said gate of said P-channel transistor connected to said reference potential; first and second N-channel transistors, each having a source-drain path and having a gate, said source-drain paths of said first and second N-channel transistors connected in series between said output and said reference potential, said gate of said first N-channel transistor connected to a said input; third and fourth N-channel transistors, each having a source-drain path and having a gate, said source-drain paths of said third and fourth N-channel transistors connected in series between said output and said reference potential, said gate of said third N-channel transistor connected to a said inverted input; and first and second N-channel leaker devices, each having a source-drain path and having a gate, said source-drain path of said first N-channel leaker device connected between a said inverted input and said gate of said second N-channel transistor, said gate of said first N-channel leaker device connected to a said input, said source-drain path of said second N-channel leaker device connected between a said input and said gate of said fourth N-channel transistor, and said gate of said second N-channel leaker device connected to a said inverted input.

Claim 12

A circuit for detecting transitions in voltage at a terminal of an integrate logic array, the circuit comprising: a supply voltage; a reference potential; at least one input having a signal corresponding to said transitions in voltage; at least one inverted input having a second signal corresponding to inversions of said transitions in voltage; an output for providing an output voltage upon detection of one of a said transition of said inversions; a P-channel transistor having a source-drain path and having a gate, said source-drain path of said P-channel transistor connected between said supply voltage and said output, said gate of said P-channel transistor connected to said reference potential; first and second N-channel transistors, each having a source-drain path and having a gate, said source-drain paths of said first and second N-channel transistors connected in series between said output and said reference potential, said gate of said first N-channel transistor connected to a said input; third and fourth N-channel transistors, each having a source-drain path and having a gate, said source-drain paths of said third and fourth N-channel transistors connected in series between said output and said reference potential, said gate of said third N-channel transistor connected to a said inverted input; and first and second N-channel leaker devices, each having a source-drain path and having a gate, said source-drain path of said first N-channel leaker device connected between a said inverted input and said gate of said second N-channel transistor, said gate of said first N-channel leaker device connected to a said input, said source-drain path of said second N-channel leaker device connected between a said input and said gate of said fourth N-channel transistor, and said gate of said second N-channel leaker device connected to a said inverted input.

Claim 13

The circuit of claim 10, including a first risetime control device having a source-drain path and having a gate, said source-drain path of said first risetime control device connected between said supply voltage and said gate of said second N-channel transistor, said gate of said first risetime control device connected to a said input, and a second risetime control device having a source-drain path and having a gate, said source-drain path of said second risetime control device connected between said supply voltage and said gate of said fourth N-channel transistor, said gate of said second risetime control device connected to a said inverted input.

Claim 14

The circuit of claim 10, including a first risetime control transistor of a predetermined conductivity-type having a source-drain path and having a gate, said source-drain path of said first risetime control transistor connected between said supply voltage and said gate of said second N-channel transistor, said gate of said first risetime control transistor connected to a said input, and a second risetime control transistor of said predetermined conductivity-type having source-drain path and having a gate, said source-drain path of said second risetime control transistor connected between said supply voltage and said gate of said fourth N-channel transistor, said gate of said second risetime control transistor connected to a said inverted input; wherein said predetermined conductivity-type is P-type.

Claim 15

The circuit of claim 10, including a first risetime control transistor having a source-drain channel path and having a gate, said source-drain path of said first risetime control transistor having predetermined width and length, said source-drain channel path of said first risetime control transistor connected between said supply voltage and said gate of said second N-channel transistor, said gate of said first risetime control transistor connected to a said input, and a second risetime control transistor having source-drain channel path and having a gate, said source-drain path of said second risetime control transistor having predetermined width and length, said source-drain channel path of said second risetime control transistor connected between said supply voltage and said gate of said fourth N-channel transistor, said gate of said second risetime control transistor connected to a said inverted input; wherein said risetime of said output voltage at said output is determined by said predetermined source-drain channel path widths and lengths of said first and second risetime control transistors.

Claim 16

The circuit of clam 10, wherein said first and second leaker devices are N-channel field-effect transistors.

Claim 17

The circuit of clam 10, wherein said first and second leaker devices are N-channel field-effect transistors.

Claim 18

The circuit of claim 10, wherein the duration of said output voltage at said output is determined by the widths and lengths of said source-drain paths of said first and second leaker devices.

Claim 19

The circuit of clam 10, including an inverter having an input, said input of said inverter connected to said output of said circuit.

Claim 20

The circuit of clam 10, including an inverter having an input, said input of said inverter connected to said output of said circuit.

Claim 21

The circuit of clam 10, including an inverter having an input and having an output, said input of said inverter connected to said output of said circuit; and a NOR circuit having an input, said input of said NOR circuit connected to said output of said inverter.

Claim 22

The circuit of clam 10, including an inverter having an input and having an output, said input of said inverter connected to said output of said circuit; and a NOR circuit having an input, said input of said NOR circuit connected to said output of said inverter.

Claim 23

The circuit of claim 10, including an inverter having an input and having an output, said input of said inverter connected to said output of said circuits; a NOR circuit having an input and having an output, said input of said NOR circuit connected to said output of said inverter; and a NAND circuit having an input, said input of said NAND circuit connected to said output of said NOR circuit.

Claim 24

A circuit for detecting transitions in voltage at a terminal of an integrated logic array, the circuit comprising: a supply voltage; a reference potential; at least one input having a signal corresponding to one of said transitions in voltage; at least one inverted input having a signal corresponding to an inversion of said one transition in voltage; an output for providing an output voltage upon detection of one of said transitions or said inversions; a first P-channel transistor having source-drain path and having a gate, said source-drain path of said first P-channel transistor connected between said supply voltage and said output, said gate of said first P-channel transistor connected to said reference potential; first and second N-channel transistors, each having a source-drain path and having a gate, said source-drain paths of said first and second N-channel transistors connected in series between said output and said reference potential, said gate of said first N-channel transistor connected to a said input; a second P-channel transistor and a third N-channel transistor, each having a source-drain path and having a gate, said source-drain paths of said second P-channel transistor and of said third N-channel transistor connected in series between said output and said reference potential, said gate of said second P-channel transistor connected to a said input; and first and second n-channel leaker devices, each having a source-drain path and having a gate, said source-drain path of said first N-channel leaker device connected between a said inverted input and said gate of said second N-channel transistor, said gate of said first N-channel leaker device connected to a said input signal, said source-drain path of said second N-channel leaker device connected between a said input and said gate of said third N-channel transistor, said gate of said second N-channel leaker device connected to a said inverted input.

Claim 25

A circuit for detecting transitions in voltage at a terminal of an integrated logic array, the circuit comprising: a supply voltage; a reference potential; at least one input having a signal corresponding to one of said transitions in voltage; at least one inverted input having a signal corresponding to an inversion of said one transition in voltage; an output for providing an output voltage upon detection of one of said transitions or said inversions; a first P-channel transistor having source-drain path and having a gate, said source-drain path of said first P-channel transistor connected between said supply voltage and said output, said gate of said first P-channel transistor connected to said reference potential; first and second N-channel transistors, each having a source-drain path and having a gate, said source-drain paths of said first and second N-channel transistors connected in series between said output and said reference potential, said gate of said first N-channel transistor connected to a said input; a second P-channel transistor and a third N-channel transistor, each having a source-drain path and having a gate, said source-drain paths of said second P-channel transistor and of said third N-channel transistor connected in series between said output and said reference potential, said gate of said second P-channel transistor connected to a said input; and first and second n-channel leaker devices, each having a source-drain path and having a gate, said source-drain path of said first N-channel leaker device connected between a said inverted input and said gate of said second N-channel transistor, said gate of said first N-channel leaker device connected to a said input signal, said source-drain path of said second N-channel leaker device connected between a said input and said gate of said third N-channel transistor, said gate of said second N-channel leaker device connected to a said inverted input.

Claim 26

The circuit of claim 19, including a first risetime control device having a source-drain path and having a gate, said source-drain path of said first risetime control device connected between said supply voltage and said gate of said second N-channel transistor, said gate of said first risetime control device connected to a said input, and a second risetime control device having a source-drain path and having a gate, said source-drain path of said second risetime control device connected between said supply voltage and said gate of said third N-channel transistor, said gate of said second risetime control device connected to a said inverted input.

Claim 27

The circuit of claim 19, including a first risetime control transistor of a predetermined conductivity-type having source-drain path and having a gate, said source-drain path of said first risetime control transistor connected between said supply voltage and said gate of said second N-channel transistor, said gate of said first risetime control transistor, said gate of said first risetime control transistor connected to a said input; and a second risetime control transistor of said predetermined conductivity-type having a source-drain path and having a gate, said source-drain path of said second risetime control transistor connected between said supply voltage and said gate of said third N-channel transistor, said gate of said second risetime control transistor connected to a said inverted input; wherein said predetermined conductivity-type is P-type.

Claim 28

The circuit of claim 19, including a first risetime control transistor having source-drain channel path and having a gate, said source-drain path of said first risetime control transistor having predetermined width and length, said source-drain channel path of said first risetime control transistor connected between said supply voltage and said gate of said second N-channel transistor, said gate of said first risetime control transistor connected to a said input; and a second risetime control transistor having source-drain channel path and having a gate, said source-drain path of said second risetime control transistor having a predetermined width and length, said source-drain channel path of said second risetime control transistor connected between said supply voltage and said gate of said third N-channel transistor, said gate of said second risetime control transistor connected to a said inverted input; wherein said risetime of said output voltage at said output is determined by said predetermined source-drain channel path widths and lengths of said first and second risetime control transistors.

Claim 29

The circuit of claim 19, wherein said first and second leaker devices are N-channel field-effect transistors.

Claim 30

The circuit of clam 19, wherein the duration of said output voltage at said output is determined by the widths and lengths of said source-drain paths of said first and second leaker devices.

Claim 31

The circuit of clam 19, wherein the duration of said output voltage at said output is determined by the widths and lengths of said source-drain paths of said first and second leaker devices.

Claim 32

The circuit of clam 19, including an inverter having an input, said input of said inverter connected to said output of said circuit.

Claim 33

The circuit of clam 19, including an inverter having an input, said input of said inverter connected to said output of said circuit.

Claim 34

The circuit of claim 19, including an inverter having an input and having an output, said input of said inverter connected to said output of said circuit; and a NOR circuit having an input, said input of said NOR circuit connected to said output of said inverter.

Claim 35

The circuit of claim 19, including an inverter having an input and having an output, said input of said inverter connected to said output of said circuit; a NOR circuit having an input and having an output, said input of said NOR circuit connected to said output of said inverter; and a NAND circuit having an input, said input of said NAND circuit connected to said output of said NOR circuit.