US4649290A
Expired / Lapsed
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Pulse generating circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1985-08-15
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Granted: 1987-03-10
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Expires: 2005-08-15
Abstract
Abstract A pulse generating circuit composed of MOS IGFETs formed on a semiconductor substrate. The circuit includes first and second input circuits, each composed of an enhancement/depletion transistor pair, with the drains of each pair coupled in common to a respective one of two input terminals receiving complementary input signals. The channel resistance in the on state of the depletion-type transistors is made to be significantly higher than the channel resistance of the enhancement-type transistors in the on state. An output circuit is provided composed of a depletion-type transistor and two enhancement-type transistors connected in a NOR gate configuration. The gates of the two enhancement-type transistors of the output circuit are connected to source nodes of respective ones of the input circuits, to each of which both sources and gates of the two transistors of the respective circuit are connected.
Inventors
- 👤 Makoto Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:16
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/1534
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
87 words
A pulse generating circuit comprising: at least one input circuit and an output circuit, said input circuit comprising a transistor pair of an enhancement-type transistor and a depletion-type transistor, drain terminals of said enhancement- and depletion-type transistors being coupled to an input terminal, and gate and source terminals of said enhancement- and depletion-type transistors being coupled to a common source node, and said output circuit comprising at least one transistor having a gate coupled to said source node and an output electrode coupled to an output terminal.
Claim 2
Dependent Claim
87 words
A pulse generating circuit comprising: at least one input circuit and an output circuit, said input circuit comprising a transistor pair of an enhancement-type transistor and a depletion-type transistor, drain terminals of said enhancement- and depletion-type transistors being coupled to an input terminal, and gate and source terminals of said enhancement- and depletion-type transistors being coupled to a common source node, and said output circuit comprising at least one transistor having a gate coupled to said source node and an output electrode coupled to an output terminal.
Claim 3
Dependent Claim
17 words
The pulse generating circuit of claim 1, wherein each of said transistors is an N-channel MOS transistor.
Claim 4
Dependent Claim
37 words
The pulse generating circuit as claimed in claim 1, wherein a channel resistance of said depletion-type transistor in an on state thereof is higher than a channel resistance of said enhancement-type transistor in an on state thereof.
Claim 5
Dependent Claim
136 words
A pulse generating circuit comprising: first and second input terminals receiving an input signal and an input signal inverted, respectively; first and second input circuits, each of said input circuits comprising an enhancement/depletion transistor pair, a drain of each said enhancement-type transistor and each said depletion-type transistor being coupled commonly to a respective one of said input terminals, and gates and sources of said enhancement- and depletion-type transistors being coupled to a respective common source node; and an output circuit comprising a depletion-type transistor and two enhancement-type transistors connected in a NOR gate configuration with a common node point of said depletion-type transistor and said enhancement-type transistors of said output circuit being coupled to an output terminal, and gates of said enhancement-type transistors of said output circuit being coupled to respective ones of said source nodes.
Claim 6
Dependent Claim
136 words
A pulse generating circuit comprising: first and second input terminals receiving an input signal and an input signal inverted, respectively; first and second input circuits, each of said input circuits comprising an enhancement/depletion transistor pair, a drain of each said enhancement-type transistor and each said depletion-type transistor being coupled commonly to a respective one of said input terminals, and gates and sources of said enhancement- and depletion-type transistors being coupled to a respective common source node; and an output circuit comprising a depletion-type transistor and two enhancement-type transistors connected in a NOR gate configuration with a common node point of said depletion-type transistor and said enhancement-type transistors of said output circuit being coupled to an output terminal, and gates of said enhancement-type transistors of said output circuit being coupled to respective ones of said source nodes.
Claim 7
Dependent Claim
17 words
The pulse generating circuit of claim 4, wherein each of said transistors is an N-channel MOS transistor.
Claim 8
Dependent Claim
43 words
The pulse generating circuit of claim 4, wherein a channel resistance of said depletion-type transistors of said input circuits in an on state thereof is higher than a channel resistance of said enhancement-type transistors of said input circuits in an on state thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-09 | 1990-09-08 | 1991-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-09 | 1994-09-08 | 1995-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-09 | 1998-09-08 | 1999-03-10 | $7700.00 | Window Closed / Lapsed |