Method of anti-fuse repair

Claim 2

An integrated circuit comprising: an anti-fuse having first and second plates separated by a layer of dielectric; programming circuitry adapted to couple a first potential to the first plate; and a virtual ground coupled to the second plate for providing a second potential to the second plate, such that a differential voltage between the first and second plates is sufficient to create a conductive path through the dielectric.

Claim 3

An integrated circuit comprising: an anti-fuse having first and second conductive plates; a layer of oxide fabricated between the first and second conductive plates; anti-fuse logic circuitry connected to the first conductive plate for selectively coupling the first conductive plate to a program voltage level; and a bias circuit connected to the second conductive plate for coupling the second conductive plate to a ground voltage level; an external connection connected to the second conductive plate for coupling the second conductive plate to a pre-determined external voltage level during anti-fuse programming, the pre-determined external voltage level being non-zero.

Claim 4

An integrated circuit comprising: an anti-fuse having first and second conductive plates; a layer of oxide fabricated between the first and second conductive plates; anti-fuse logic circuitry connected to the first conductive plate for selectively coupling the first conductive plate to a program voltage level; and a bias circuit connected to the second conductive plate for coupling the second conductive plate to a ground voltage level; an external connection connected to the second conductive plate for coupling the second conductive plate to a pre-determined external voltage level during anti-fuse programming, the pre-determined external voltage level being non-zero.

Claim 5

The integrated circuit of claim 2 wherein the first conductive plate is a layer of polysilicon formed on the layer of oxide.

Claim 6

The integrated circuit of claim 3 wherein the layer of polysilicon is n-type.

Claim 7

The integrated circuit of claim 2 wherein the second conductive plate is a well formed in a silicon substrate.

Claim 8

The integrated circuit of claim 5 wherein the well is n-type and the silicon substrate is p-type.

Claim 9

The integrated circuit of claim 2 wherein the bias circuit comprises a transistor having a first connection coupled to the second conductive plate and a second connection coupled to the ground voltage.

Claim 10

An integrated circuit comprising: an anti-fuse having first and second conductive plates; a layer of oxide fabricated between the first and second conductive plates; anti-fuse logic circuitry connected to the first conductive plate for selectively coupling the first conductive plate to a program voltage level; an external connection connected to the second conductive plate for coupling the second conductive plate to a pre-determined external voltage level during anti-fuse programming, the pre-determined external voltage level being non-zero; a bias circuit connected to the second conductive plate for coupling the second conductive plate to a bias voltage level; and the bias circuit comprises: a transistor having a first connection coupled to the second conductive plate and a second connection coupled to a bias voltage connection to define a current path from the bias voltage connection to the second conductive plate; and a resistor located electrically in the current path between the bias voltage connection to the second conductive plate.

Claim 11

An integrated circuit comprising: an anti-fuse having first and second conductive plates; a layer of oxide fabricated between the first and second conductive plates; anti-fuse logic circuitry connected to the first conductive plate for selectively coupling the first conductive plate to a program voltage level; an external connection connected to the second conductive plate for coupling the second conductive plate to a pre-determined external voltage level during anti-fuse programming, the pre-determined external voltage level being non-zero; a bias circuit connected to the second conductive plate for coupling the second conductive plate to a bias voltage level; and the bias circuit comprises: a transistor having a first connection coupled to the second conductive plate and a second connection coupled to a bias voltage connection to define a current path from the bias voltage connection to the second conductive plate; and a resistor located electrically in the current path between the bias voltage connection to the second conductive plate.

Claim 12

An integrated circuit comprising: an anti-fuse having first and second conductive plates; a layer of oxide fabricated between the first and second conductive plates; anti-fuse logic circuitry connected to the first conductive plate for selectively coupling the first conductive plate to a program voltage level; an external connection connected to the second conductive plate for coupling the second conductive plate to a pre-determined external voltage level during anti-fuse programming, the pre-determined external voltage level being non-zero; a bias circuit connected to the second conductive plate for coupling the second conductive plate to a bias voltage level; and wherein the bias circuit comprises a plurality of transistors connected in series between the second conductive plate and the bias voltage level.

Claim 13

An integrated circuit comprising: an anti-fuse having first and second conductive plates; a layer of oxide fabricated between the first and second conductive plates; anti-fuse logic circuitry connected to the first conductive plate for selectively coupling the first conductive plate to a program voltage level; an external connection connected to the second conductive plate for coupling the second conductive plate to a pre-determined external voltage level during anti-fuse programming, the pre-determined external voltage level being non-zero; a bias circuit connected to the second conductive plate for coupling the second conductive plate to a bias voltage level; and wherein the bias circuit comprises a plurality of transistors connected in series between the second conductive plate and the bias voltage level.

Claim 14

The integrated circuit of claim 2 wherein the integrated circuit device is a memory device.

Claim 15

The integrated circuit of claim 10 wherein the memory device is a static random access memory (SRAM) having redundant memory element circuitry.

Claim 16

The integrated circuit of claim 2 wherein the program voltage level is zero potential and the external voltage is positive potential.

Claim 17

An integrated circuit memory device comprising: an anti-fuse comprising a layer of oxide fabricated between an n-type polysilicon layer and an n-well formed in a substrate; program circuitry connected to the n-type polysilicon layer for providing a program voltage to the n-type polysilicon layer; an external connection coupled to the n-well for providing an external voltage to the n-well; and a bias circuit connected to the n-well for coupling the n-well to a ground voltage.

Claim 18

An integrated circuit memory device comprising: an anti-fuse comprising a layer of oxide fabricated between an n-type polysilicon layer and an n-well formed in a substrate; program circuitry connected to the n-type polysilicon layer for providing a program voltage to the n-type polysilicon layer; an external connection coupled to the n-well for providing an external voltage to the n-well; and a bias circuit connected to the n-well for coupling the n-well to a ground voltage.

Claim 19

The integrated memory circuit of claim 13 wherein the bias circuit comprises a first transistor having a first connection coupled to the n-well and a second connection coupled to the bias voltage.

Claim 20

The integrated memory circuit of claim 14 wherein the bias circuit further comprises a second transistor connected between the second connection of the first transistor and the bias voltage.

Claim 21

The integrated memory circuit of claim 13 wherein the integrated memory circuit is a static random access memory (SRAM) having redundant memory element circuitry.

Claim 22

The integrated memory circuit of claim 13 wherein the program voltage level is zero potential and the external voltage is positive potential.

Claim 23

An integrated circuit memory device comprising: an external connection coupled to an anti-fuse comprising a layer of oxide fabricated between a polysilicon layer and a well formed in a substrate, and a bias circuit connected to the well for coupling the well to a ground voltage; and program circuitry connected to the polysilicon layer for providing a program voltage to the polysilicon layer.

Claim 24

An integrated circuit memory device comprising: an external connection coupled to an anti-fuse comprising a layer of oxide fabricated between a polysilicon layer and a well formed in a substrate, and a bias circuit connected to the well for coupling the well to a ground voltage; and program circuitry connected to the polysilicon layer for providing a program voltage to the polysilicon layer.

Claim 27

The method of claim 19 wherein the first conductive layer is fabricated as a polysilicon layer, and the second conductive plate is fabricated as a well in a silicon substrate.

Claim 28

The method of claim 19 wherein the program voltage is zero potential, and the opposite voltage is a pre-determined positive potential.

Claim 29

The method of claim 19 wherein the integrated circuit device is a memory.