US5506518A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Antifuse-based programmable logic circuit
Assignee: Xilinx Inc
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Filing: 1994-09-20
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Granted: 1996-04-09
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Expires: 2014-09-20
Abstract
Abstract The present invention provides a programmable logic circuit including a first set of lines coupled to a logic module, a second set of lines, and a plurality of transistors. Each transistor in the array has a first terminal, a second terminal, and a third terminal, wherein the first terminal is coupled to one of the first set of lines and the second terminal is coupled to one of the second set of lines. In accordance with the present invention, an antifuse is coupled between the third terminal of the transistor and a voltage source. By selectively programming antifuses in the array and selectively turning on transistors, complex user functions with a large number of inputs are implemented in one pass.
Inventors
- 👤 David Chiang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17744; G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; H03K19/17704
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
94 words
A programmable logic circuit coupled to a logic module, said logic circuit comprising: a first set of lines coupled to said logic module; a second set of lines; a plurality of transistors, each transistor having a first terminal, a second terminal, and a third terminal, wherein said first terminal is coupled to one of said first set of lines and said second terminal is coupled to one of said second set of lines; and a plurality of antifuses, each antifuse coupled between said third terminal of one of said transistors and a voltage source.
Claim 2
Dependent Claim
94 words
A programmable logic circuit coupled to a logic module, said logic circuit comprising: a first set of lines coupled to said logic module; a second set of lines; a plurality of transistors, each transistor having a first terminal, a second terminal, and a third terminal, wherein said first terminal is coupled to one of said first set of lines and said second terminal is coupled to one of said second set of lines; and a plurality of antifuses, each antifuse coupled between said third terminal of one of said transistors and a voltage source.
Claim 3
Dependent Claim
15 words
The circuit of claim 1 wherein said first terminal of said transistor is a drain.
Claim 4
Dependent Claim
15 words
The circuit of claim 2 wherein said second terminal of said transistor is a gate.
Claim 5
Dependent Claim
15 words
The circuit of claim 3 wherein said third terminal of said transistor is a source.
Claim 6
Dependent Claim
11 words
The circuit of claim 1 wherein said voltage source is ground.
Claim 7
Dependent Claim
14 words
The circuit of claim 1 wherein at least one of said antifuses is programmed.
Claim 8
Dependent Claim
22 words
The circuit of claim 1 further including a plurality of amplifiers coupled between said first set of lines and said logic module.
Claim 9
Independent Claim
59 words
A method of increasing fanin functionality in a logic circuit comprising the steps of: coupling a first line to a logic module; coupling a first terminal of a transistor to said first line; coupling a second terminal of said transistor to a second line; and coupling an antifuse between a third terminal of said transistor and a voltage source.
Claim 10
Independent Claim
59 words
A method of increasing fanin functionality in a logic circuit comprising the steps of: coupling a first line to a logic module; coupling a first terminal of a transistor to said first line; coupling a second terminal of said transistor to a second line; and coupling an antifuse between a third terminal of said transistor and a voltage source.
Claim 11
Dependent Claim
13 words
The method of claim 8 further including the step of programing said antifuse.
Claim 12
Dependent Claim
21 words
The method of claim 8 further including the step of coupling an amplifier between said first line and said logic module.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-09 | 1999-10-09 | 2000-04-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-09 | 2003-10-09 | 2004-04-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-09 | 2007-10-09 | 2008-04-09 | $7700.00 | Window Closed / Lapsed |