Integrated chip multilayer decoupling capacitors

Claim 1

A multilayer circuit for providing decoupling capacitors for an integrated circuit formed in a semiconductor substrate, comprising: a first capacitor n well electrode supported by the substrate; a first and second n+ areas formed on opposite sides of the n well electrode supported by the substrate; a second capacitor electrode formed of a conductive material at least partially overlaying the first electrode between the first and second n+ areas; a first dielectric layer formed between the first and second capacitor electrodes; a third bifurcated capacitor electrode formed of a conductive material, the third capacitor electrode comprising a first portion laterally separated from a second portion, each portion at least partially overlaying the second electrode, and wherein the first portion is coupled to the first n+ area; a second dielectric layer formed between the second and third capacitor electrodes; a third n+ area supported by the substrate, and isolated from the first and second n+ areas, said third n+ area being electrically coupled to the second portion of the third bifurcated capacitor electrode; a fourth capacitor electrode formed of a conductive material at least partially overlaying the third bifurcated capacitor electrode; and a third dielectric layer disposed between the third and fourth electrodes such that pairs of electrodes at least partially overlaying each other may be coupled to operate as decoupling capacitors.