Method of preventing storage node to storage node shorts in fabrication of memory integrated circuitry having stacked capacitors and stacked capacitor memory integrated circuits

Claim 1

A semiconductor processing method of fabricating memory integrated circuitry having stacked capacitors, the method comprising the following steps: fabricating a semiconductor wafer to provide a pair of adjacent, substantially parallel and spaced word lines and to define regions for formation of stacked storage node capacitors and buried contacts therefor, the individual stacked capacitors overlapping the pair of adjacent word lines; the pair of adjacent word lines including first separation regions therebetween within which storage node capacitors and respective buried contacts are provided, the pair of adjacent word lines including second separation regions therebetween, the first and second separation regions alternating relative to one another between and along the substantially parallel and separated word lines, the first separation regions having a first separation distance which defines the spacing between the pair of word lines in the first separation regions, the second separation regions having a second separation distance which defines the spacing between the pair of word lines in the second separation regions, the second separation distance being less than the first separation distance; providing an insulating layer to a first selected thickness atop the wafer and between the pair of word lines, the first selected thickness being greater than one-half the second separation distance to fill the second separation regions between the pair of word lines with insulating material, the first selected thickness being less than one-half the first separation distance to provide a space within the first separation regions between the pair of word lines, the space having a width; selectively removing portions of the insulating layer within the first separation regions to define buried contacts to underlying substrate; depositing a layer of conductive material to a second selected thickness atop the wafer and within the space; patterning the layer of conductive material to define lower storage node capacitor plates; and providing a capacitor dielectric and upper storage node capacitor plates above the lower storage node capacitor plates.