US5737764A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Generation of memory column addresses using memory array type bits in a control register of a computer system
Assignee: Texas Instruments Inc
•
Filing: 1995-06-07
•
Granted: 1998-04-07
•
Expires: 2015-06-07
Abstract
Abstract A method and circuitry for generating column addresses for a memory based upon signals on an address bus in a computer system, are disclosed. The disclosed circuitry is provided within a memory controller unit of a microprocessor unit, and includes circuitry for receiving address lines from the address bus, and for receiving control register bits indicating a particular memory array type. The memory array type indicates the number of the address bits which are to be forwarded to the memory as the column address, rather than as the row address. The memory is of a dynamic random access memory (DRAM) type, for which row and column addresses are time-multiplexed over the same lines. The microprocessor unit may be integrated onto a single integrated circuit chip with the memory controller, and may include a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes circuitry for controlling the access to configuration registers, and circuitry for determining the sizes of individual memory banks in the memory.
Inventors
- 👤 Akio Shigeeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:31
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/16; G06F1/1613; G06F1/1615; G06F1/1616; G06F1/1632; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F12/0684; G06F12/08; G06F12/0802; G06F12/0804; G06F12/0893; G06F12/0897; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1441; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1636; G06F13/1668; G06F13/1694; G11; G11C; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
94 words
A memory controller circuit for generating column addresses from addresses communicated on a bus, comprising: a control register for storing a memory array type code indicating a particular one of a plurality of memory array types; and a column address selector circuit having inputs receiving a plurality of address lines of the bus, having outputs, and having control inputs receiving the contents of said control register, for selectively communicating a number of the address lines to its outputs as a column address responsive to the memory array type code stored in said control register.
Claim 2
Dependent Claim
94 words
A memory controller circuit for generating column addresses from addresses communicated on a bus, comprising: a control register for storing a memory array type code indicating a particular one of a plurality of memory array types; and a column address selector circuit having inputs receiving a plurality of address lines of the bus, having outputs, and having control inputs receiving the contents of said control register, for selectively communicating a number of the address lines to its outputs as a column address responsive to the memory array type code stored in said control register.
Claim 3
Dependent Claim
114 words
The circuit of claim 1 wherein said control register comprises a plurality of locations, each control register location storing a memory array type code associated with one of a plurality of banks of a memory to be addressed by the column addresses; and further comprising: a bank control selector having inputs coupled to each of the locations of the control register, having outputs coupled to the control inputs of the column address selector circuit, and having control inputs receiving a bank identification signal, the bank control selector for selectively passing, to the control inputs of the column address selector circuit, the memory array type code for the bank identified by the bank identification signal.
Claim 4
Dependent Claim
64 words
The circuit of claim 1 further comprising: a row address selector circuit having inputs receiving a plurality of address lines of the bus, having outputs, and having control inputs receiving the contents of said control register, for selectively communicating a number of the address lines to its outputs as a row address responsive to the memory array type code stored in said control register.
Claim 5
Dependent Claim
138 words
The circuit of claim 3 wherein said control register comprises a plurality of locations, each control register location storing a memory array type code associated with one of a plurality of banks of a memory to be addressed by the row and column addresses; and further comprising: a bank control selector having inputs coupled to each of the locations of the control register, having outputs coupled to the control inputs of the column address selector circuit and to the control inputs of the row address selector circuit, and having control inputs receiving a bank identification signal, the bank control selector for selectively passing, to the control inputs of the column address selector circuit and to the control inputs of the row address selector circuit, the memory array type code for the bank identified by the bank identification signal.
Claim 6
Dependent Claim
41 words
The circuit of claim 3 further comprising a row/column address multiplexer having inputs connected to the outputs of the column address selector circuit and to the outputs of the row address selector circuit, and having outputs to supply multiplexed row/column addresses.
Claim 7
Dependent Claim
89 words
The circuit of claim 1, wherein the column address selector circuit has a first set of inputs coupled to address lines of the bus, and has a second set of inputs including at least one input connected to a fixed level; and wherein the column address selector circuit communicates its first set of inputs to its outputs responsive to the memory array type code having a first value, and communicates its second set of inputs to its outputs responsive to the memory array type code having a second value.
Claim 8
Dependent Claim
38 words
The circuit of claim 6, wherein the column address selector circuit forwards a least-significant group of address lines of the bus to its outputs responsive to the memory array type code having either the first or second value.
Claim 9
Independent Claim
115 words
A method of operating a memory controller circuit to generate row and column addresses for a memory, comprising the steps of: storing a memory array type code in a control register, the memory array type code indicating a particular one of a plurality of memory array types; receiving a memory address on a plurality of address lines of a bus; generating a row address from a first plurality of address lines of the bus, selected responsive to the memory array type code stored in the control register; and generating a column address from a second plurality of address lines of the bus, selected responsive to the memory array type code stored in the control register.
Claim 10
Independent Claim
115 words
A method of operating a memory controller circuit to generate row and column addresses for a memory, comprising the steps of: storing a memory array type code in a control register, the memory array type code indicating a particular one of a plurality of memory array types; receiving a memory address on a plurality of address lines of a bus; generating a row address from a first plurality of address lines of the bus, selected responsive to the memory array type code stored in the control register; and generating a column address from a second plurality of address lines of the bus, selected responsive to the memory array type code stored in the control register.
Claim 11
Dependent Claim
28 words
The method of claim 8 wherein the memory array type code indicates the number of column address bits to be applied to the memory in a memory access.
Claim 12
Dependent Claim
74 words
The method of claim 8, wherein the memory is arranged in a plurality of banks; wherein the storing step comprises storing a memory array type code in each of a plurality of locations of the control register, each location associated with one of the plurality of banks of the memory; and further comprising: before the generating steps, selecting one of the plurality of locations of the control register responsive to a bank select signal.
Claim 13
Dependent Claim
22 words
The method of claim 8, further comprising: applying the row address to a memory; and applying the column address to the memory.
Claim 14
Dependent Claim
26 words
The method of claim 8, further comprising: applying the row address to a memory address bus; and applying the column address to the memory address bus.
Claim 15
Dependent Claim
23 words
The method of claim 12, wherein the step of applying the column address is performed after the step of applying the row address.
Claim 16
Dependent Claim
102 words
The method of claim 8, wherein the step of generating a column address comprises: generating a first portion of the column address from a first group of address lines of the bus; generating a second portion of the column address, the second portion being of greater significance than the first portion, from a second group of address lines of the bus responsive to the memory array type code having a first value; and generating the second portion of the column address to have at least one bit with a fixed value responsive to the memory array type code having a second value.
Claim 17
Dependent Claim
80 words
The method of claim 14, wherein the step of generating a row address comprises: selecting a third group of address lines of the bus responsive to the memory array type code having the first value; and selecting a fourth group of address lines of the bus, the second group having at least one address line of the bus not within the first group of address lines of the bus, responsive to the memory array type code having the second value.
References Cited (Backward Citations)
US4739473A
Cited
US5040153A
Cited
US5513331A
Cited
US5237672A
Cited
US5317709A
Cited
US5408129A
Cited
US5287531A
Cited
US5301292A
Cited
US5274768A
Cited
US5572692A
Cited
US5307320A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-06 | 2001-10-06 | 2002-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-06 | 2005-10-06 | 2006-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-06 | 2009-10-06 | 2010-04-07 | $7700.00 | Window Closed / Lapsed |