US5301292A
Expired / Lapsed
US
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Page mode comparator decode logic for variable size DRAM types and different interleave options
Assignee: NXP BV
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Filing: 1991-02-22
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Granted: 1994-04-05
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Expires: 2011-02-22
Abstract
Abstract Apparatus for decoding and comparing memory addresses which determines DRAM size and interleave options utilized is disclosed. A row address and bank select bits are decoded and latched and are subsequently compared with the address during the next memory cycle. If the next address matches the address stored in the latch, a "page hit" occurs and the memory cycle is shortened since the addresses during the consecutive memory address will differ only in the column address.
Inventors
- 👤 William K. Hilton
- 👤 Albert J. Weidner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:15
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0607; G06F12/0215
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
294 words
In a computer system containing a plurality of dynamic random access memories of different sizes, a page hit mode detection system for providing both two way and four way interleaving and word type and byte type interleaving comprising, in combination: control logic means containing memory map configuration data and interleaving option data stored therein for providing an output on each of a plurality of enable signal lines; first latch means couples to a first plurality of address lines of a portion of said plurality of dynamic random access memories for storing a plurality of first address signals that are applied to said first plurality of address lines; multiplexer means coupled to a second plurality of address lines of another portion of said plurality of dynamic random access memories and to said enable signal lines of said control logic means for providing a plurality of multiplexed address signals in response to said output on each of said plurality of signal lines; second latch means coupled to outputs of said multiplexer means for storing a plurality of multiplexed signals, said first and second latch means being connected to an input signal line having an update compare signal thereon, said first plurality of address signals and said multiplexed address signals being stored within said first and second latch means, respectively, in response to said update-compare signal; comparing means coupled to said first and second latch means, said first plurality of address lines, and to said multiplexer means for providing a comparison output signal which is dependent upon inputs to said comparison means; and page hit means coupled to said comparing means and a signal line that provides a memory cycle signal for generating an output page hit signal in response to said inputs to said comparing means.
Claim 2
Dependent Claim
294 words
In a computer system containing a plurality of dynamic random access memories of different sizes, a page hit mode detection system for providing both two way and four way interleaving and word type and byte type interleaving comprising, in combination: control logic means containing memory map configuration data and interleaving option data stored therein for providing an output on each of a plurality of enable signal lines; first latch means couples to a first plurality of address lines of a portion of said plurality of dynamic random access memories for storing a plurality of first address signals that are applied to said first plurality of address lines; multiplexer means coupled to a second plurality of address lines of another portion of said plurality of dynamic random access memories and to said enable signal lines of said control logic means for providing a plurality of multiplexed address signals in response to said output on each of said plurality of signal lines; second latch means coupled to outputs of said multiplexer means for storing a plurality of multiplexed signals, said first and second latch means being connected to an input signal line having an update compare signal thereon, said first plurality of address signals and said multiplexed address signals being stored within said first and second latch means, respectively, in response to said update-compare signal; comparing means coupled to said first and second latch means, said first plurality of address lines, and to said multiplexer means for providing a comparison output signal which is dependent upon inputs to said comparison means; and page hit means coupled to said comparing means and a signal line that provides a memory cycle signal for generating an output page hit signal in response to said inputs to said comparing means.
Claim 3
Dependent Claim
18 words
The system of claim 1 wherein said comparing means includes EXCLUSIVE-NOR means for providing said comparison output signal.
Claim 4
Dependent Claim
13 words
The system of claim 2 wherein said EXCLUSIVE-NOR means includes an EXCLUSIVE-NOR gate.
Claim 5
Dependent Claim
19 words
The system of claim 3 wherein said comparison means comprises a NAND gate coupled to said page hit means.
Claim 6
Dependent Claim
47 words
The system of claim 4 wherein said page hit means includes a page-hit latch having a pair of inputs respectively connected to an output of said NAND gate and to said memory cycle signal line, an output of said page hit latch providing said output page-hit signal.
Claim 7
Dependent Claim
38 words
The system of claim 5 wherein a clear page-hit signal line is connected to said page hit latch, said page hit latch being cleared in response to a clear signal being provided on said clear page-hit signal line.
Claim 8
Independent Claim
302 words
A method of providing in a computer system containing a plurality of dynamic random access memories of different sizes, a page hit mode detection system for providing both two way and four way interleaving and word type and byte type interleaving comprising the steps of: providing control logic means containing memory map configuration data and interleaving option data stored therein for providing an output on each of a plurality of enable signal lines; providing first latch means coupled to a first plurality of address lines of a portion of said plurality of dynamic random access memories for storing a plurality of first address signals that are applied to said first plurality of address lines; providing multiplexer means coupled to a second plurality of address lines of another portion of said plurality of random access memories and to said enable signal lines of said control logic means for providing a plurality of multiplexed address signals in response to said output on each of said plurality of signal lines; providing second latch means coupled to outputs of said multiplexer means for storing a plurality of multiplexed signals, said latch means being connected to an input signal line having an update compare signal thereon, said first plurality of address signals and said multiplexed address signals being stored within said first and second latch means, respectively, in response to said update-compare signal; and providing comparing means coupled to said first and second latch means, said first plurality of address lines, and to said multiplexer means for providing a comparison output signal which is dependent upon inputs to said comparison means; and providing page hit means coupled to said comparing means and a signal line that provides a memory cycle signal for generating an output page hit signal in response to said inputs to said comparing means.
Claim 9
Independent Claim
302 words
A method of providing in a computer system containing a plurality of dynamic random access memories of different sizes, a page hit mode detection system for providing both two way and four way interleaving and word type and byte type interleaving comprising the steps of: providing control logic means containing memory map configuration data and interleaving option data stored therein for providing an output on each of a plurality of enable signal lines; providing first latch means coupled to a first plurality of address lines of a portion of said plurality of dynamic random access memories for storing a plurality of first address signals that are applied to said first plurality of address lines; providing multiplexer means coupled to a second plurality of address lines of another portion of said plurality of random access memories and to said enable signal lines of said control logic means for providing a plurality of multiplexed address signals in response to said output on each of said plurality of signal lines; providing second latch means coupled to outputs of said multiplexer means for storing a plurality of multiplexed signals, said latch means being connected to an input signal line having an update compare signal thereon, said first plurality of address signals and said multiplexed address signals being stored within said first and second latch means, respectively, in response to said update-compare signal; and providing comparing means coupled to said first and second latch means, said first plurality of address lines, and to said multiplexer means for providing a comparison output signal which is dependent upon inputs to said comparison means; and providing page hit means coupled to said comparing means and a signal line that provides a memory cycle signal for generating an output page hit signal in response to said inputs to said comparing means.
Claim 10
Dependent Claim
18 words
The method of claim 7 wherein said comparing means includes EXCLUSIVE-NOR means for providing said comparison output signal.
Claim 11
Dependent Claim
13 words
The method of claim 8 wherein said EXCLUSIVE-NOR means includes an EXCLUSIVE-NOR gate.
Claim 12
Dependent Claim
19 words
The method of claim 9 wherein said comparison means comprises a NAND gate coupled to said page hit means.
Claim 13
Dependent Claim
47 words
The method of claim 10 wherein said page hit means includes a page-hit latch having a pair of inputs respectively connected to an output of said NAND gate and to said memory cycle signal line, an output of said page hit latch providing said output page-hit signal.
Claim 14
Dependent Claim
38 words
The method of claim 11 wherein a clear page-hit signal line is connected to said page hit latch, said page hit latch being cleared in response to a clear signal being provided on said clear page-hit signal line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-04 | 1997-10-04 | 1998-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-04 | 2001-10-04 | 2002-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-04 | 2005-10-04 | 2006-04-05 | $7700.00 | Window Closed / Lapsed |