Computer memory apparatus

Claim 2

A memory subsystem used in a system in which said subsystem couples to a single word bus for receiving memory requests and for transferring information words to said bus during bus cycles of operation, said memory requests including a multibit address and certain ones of said requests being coded to specify a predetermined type of memory read operation requiring a transfer of a plurality of words over successive bus cycles of operation, said memory subsystem comprising: a number of addressable single word wide memory stacks, each including a plurality of word blocks of dynamic random access memory chips mounted on a single circuit board; decode means coupled to said plurality of blocks of chips of said number of stacks and to said bus to receive a number of least significant and most significant bits of each said multibit address and an input density signal, said decode means being operative to generate a plurality of select signals, said select signals preselecting a corresponding plurality of word blocks from a common stack or from at least a pair of adjacent stacks of said number of memory stacks as a function of said input density signal; selection means coupled to said plurality of blocks of chips of said number of stacks and to receive at least one of said number of least significant bits and said input density signal; a plurality of registers coupled in common to said number of stacks; and, timing means for generating a sequence of timing signals for each predetermined read type of read operation, said timing means being coupled to said number of memory stacks, to said selection means and to said plurality of registers, said sequence of timing signals including a first timing signal having a duration for defining a first interval and a plurality of sequential timing signals which occur during said first interval, said blocks of chips preselected by said select signals being conditioned by said first timing signal for access, said plurality of timing signals being applied selectively by said selection means to different groups of blocks of chips within said common stack or at least said pair of adjacent stacks for read out of a plurality of words in tandem into said registers from said blocks preselected by said select signals within said common stack or distributed between at least said pair of adjacent stacks.

Claim 3

The subsystem of claim 1 wherein said decode means includes a number of programmable logic array (PLA) circuits, corresponding in number to one-half of said number of addressable memory stacks, each of said number of PLA circuits being programmed to generate a number of sets of select signals, each set being applied to a different predetermined one of said number of addressable memory stacks.

Claim 4

The subsystem of claim 2 wherein said number of said stacks has a value equal to two and said number of PLA circuits has a value equal to one, said one PLA circuit having first and second sets of output pins connected to first and second ones of said stacks and said PLA circuit being programmed to produce outputs on said pins according to the following Boolean equations: ______________________________________ FIRST SET: Output 1 = /1+/2+/3*/4*/5*/6; Output 2 = /1+/2+/3*/4*/5*/6*7; +3*/4*/5*/6; +/3*4*/5*/6*/7; Output 3 = /1+/2+3*/4*/5*/6*7; +/3*4*/5*/6*7; and, Output 4 = /1+/2+4*/5*/6*7; SECOND SET: Output 1 = /1+/2+/4*/5*/6*/7; +/3*/4*5*/6*/7; Output 2 = /1+/2+4*/5*/6*/7 +/4*5*/6*7; Output 3 = /1+/2+3*/4*5*/6*7 +/3*4*5*/6*7; and, Output 4 = /1+/2+4*5*/6*7; ______________________________________ wherein the symbols +, * and / have the following meanings: +=OR function; *=AND function; and, /=the designated signal is low or a binary ZERO.

Claim 5

The subsystem of claim 2 wherein said number of said stacks has a value equal to four and said number of PLA circuits has a value equal to two, a first PLA circuit having first and second sets of output pins connected respectively to first and second ones of said stacks and a second PLA circuit having first and second sets of output pins connected respectively to third and fourth ones of said stacks, said first and second PLA circuits being programmed to produce outputs on said pins according to the following Boolean equations: ______________________________________ FIRST PLA CIRCUIT: FIRST SET: Output 1 = /1+/2+/3*/4*/5*/6; Output 2 = /1+/2+/3*/4*/5*/6*7; +3*/4*/5*/6; +/3*4*/5*/6*/7; Output 3 = /1+/2+3*/4*/5*/6*7; +/3*4*/5*/6*7; and, Output 4 = /1+/2+4*/5*/6*7; SECOND SET: Output 1 = /1+/2+/4*/5*/6*/7; +/3*/4*5*/6*/7; Output 2 = /1+/2+4*/5*/6*/7 +/4*5*/6*7; Output 3 = /1+/2+3*/4*5*/6*7 +/3*4*5*/6*7; and, Output 4 = /1+/2+4*5*/6*7; SECOND PLA CIRCUIT: FIRST SET: Output 1 = /1+/2+/3*/4*5*/6*/7+/3*/4*/5*6*7; Output 2 = /1+/2+3*/4*5*/6*/7+/3*4*5*/6*/7; +/4*/5*6*7; Output 3 = /1+/2+3*/4*/5*6*7+/3*4*/5*6*7; Output 4 /1+/2+4*/5*6*7; SECOND SET: Output 1 = /1+/2+/4*5*/6*/7+/3*/4*5*6*7; Output 2 = /1+/2+4*5*/6*/7+/4*5*6*7; Output 3 = /1+/2+3*/4*5*6*7+/3*4*5*6*7; and, Output 4 = /1+/2+4*5*6*7; ______________________________________ wherein the symbols +, * and / have the following meanings: +=OR function, *=AND function; and, /=the designated signal is low or a binary ZERO.

Claim 6

The memory subsystem of claim 1 wherein said input density signal when in a first state conditions said decode means and said selection means to cause in turn each one of said number of stacks to read out said plurality of words in tandem from each one of said number of stacks.

Claim 7

The memory subsystem of claim 1 wherein said input density signal when in a second state conditions said decode means and said selection means to condition in turn a different pair of adjacent stacks to read out said plurality of words in tandem from said different pair of said adjacent stacks.

Claim 8

The memory subsystem of claim 1 wherein said selection means includes a plurality of groups of selector circuits, each selector circuit of each group being coupled to a number of said plurality of blocks of chips of a different one of said stacks, to said timing means and to receive said one of said number of least significant bits and said input density signal when in a first state indicating a common stack configuration conditioning first and second ones of each group of selector circuits in succession to apply said timing signals to said number of said plurality of blocks of chips of said different one of said stacks for read out of said plurality of words from said different one of said stacks.

Claim 9

The memory subsystem of claim 7 wherein each of said number of stacks of said common stack configuration has at least twice as many word blocks than said number of stacks organized in an adjacent stack configuration.

Claim 10

The memory subsystem of claim 7 wherein each of said selector circuits of each group are connected in common to said plurality of blocks of chips, said input density signal when in a second state indicating an adjacent stack configuration conditioning only a predetermined one of said selector circuits of each group in succession to apply said timing signals to said plurality of blocks of chips for read out of said plurality of words from adjacent stacks.

Claim 11

A memory subsystem used in a system which couples to a single word bus and receives memory requests, each request including a multibit address having first and second address portions, said subsystem comprising: a number of addressable single word wide modules connected in common to an internal bus, each including a plurality of word blocks of dynamic random access memory chips; control means coupled to said modules and to said single word bus for receiving a plurality of bits of each address and an input control signal, said address bits coded to preselect a group of blocks within said plurality of blocks of one of said modules or from adjacent ones of said modules as a function of said input control signal; selector means coupled to said number of addressable single word wide modules and to said single word bus for receiving at least a least significant bit of each address and said input control signal; a plurality of registers coupled in common to said internal bus; and, timing means for generating a sequence of timing signals in response to each predetermined type of request, said timing means being coupled to said modules, to said selector means and to said plurality of registers, a first one of said timing signals conditioning said chips of said group of blocks preselected by said address bits of said one of said modules or said adjacent ones of said modules to store said first address portion of said multibit address and second and third ones of said timing signals conditioning said selector means to cause each of said plurality of blocks of said modules to store said second address portion of said multibit address for read out of words in tandem from only said multibit address for read out of words in tandem from only said group of blocks preselected by said address bits within said one of said modules or said adjacent modules in a predetermined sequence of said plurality of registers.

Claim 12

A memory subsystem used in a system which couples to a single word bus and receives memory requests, each request including a multibit address having first and second address portions, said subsystem comprising: a number of addressable single word wide modules connected in common to an internal bus, each including a plurality of word blocks of dynamic random access memory chips; control means coupled to said modules and to said single word bus for receiving a plurality of bits of each address and an input control signal, said address bits coded to preselect a group of blocks within said plurality of blocks of one of said modules or from adjacent ones of said modules as a function of said input control signal; selector means coupled to said number of addressable single word wide modules and to said single word bus for receiving at least a least significant bit of each address and said input control signal; a plurality of registers coupled in common to said internal bus; and, timing means for generating a sequence of timing signals in response to each predetermined type of request, said timing means being coupled to said modules, to said selector means and to said plurality of registers, a first one of said timing signals conditioning said chips of said group of blocks preselected by said address bits of said one of said modules or said adjacent ones of said modules to store said first address portion of said multibit address and second and third ones of said timing signals conditioning said selector means to cause each of said plurality of blocks of said modules to store said second address portion of said multibit address for read out of words in tandem from only said multibit address for read out of words in tandem from only said group of blocks preselected by said address bits within said one of said modules or said adjacent modules in a predetermined sequence of said plurality of registers.

Claim 13

The subsystem of claim 10 wherein said control means includes a number of programmable logic array (PLA) circuits having a number of sets of outputs, each of said number of PLA circuits being programmed to generate said number of sets of select signals on said outputs, each set of outputs being applied to a different predetermined one of said number of addressable memory modules.

Claim 14

The subsystem of claim 10 wherein said control means includes a number of programmable logic array (PLA) circuits, corresponding in number to at least one-half of said number of addressable memory modules, each of said number of PLA circuits being programmed to generate said number of sets of select signals, each set being applied to a different predetermined one of said number of addressable memory modules.

Claim 15

The subsystem of claim 12 wherein said number of said modules has a value equal to two and said number of PLA circuits has a value equal to one, said one PLA circuit having first and second sets of output pins connected to first and second ones of said modules and said PLA circuit being programmed to produce outputs on said pins according to the following Boolean equations: ______________________________________ FIRST SET: Output 1 = /1+/2+/3*/4*/5*/6; Output 2 = /1+/2+/3*/4*/5*/6*7; +3*/4*/5*/6; +/3*4*/5*/6*/7; Output 3 = /1+/2+3*/4*/5*/6*7; +/3*4*/5*/6*7; and, Output 4 = /1+/2+4*/5*/6*7; SECOND SET: Output 1 = /1+/2+/4*/5*/6*/7; +/3*/4*5*/6*/7; Output 2 = /1+/2+4*/5*/6*/7 +/4*5*/6*7; Output 3 = /1+/2+3*/4*5*/6*7 +/3*4*5*/6*7; and, Output 4 = /1+/2+4*5*/6*7; ______________________________________ wherein the symbols +, * and / have the following meanings: +=OR function, *=AND function; and, /=the designated signal is low or a binary ZERO.

Claim 16

The subsystem of claim 12 wherein said number of said modules has a value equalt to four and said number of PLA circuits has a value equal to two, a first PLA circuit having first and second sets of output pins connected respectively to first and second ones of said modules and a second PLA circuit having first and second sets of output pins connected respectively to third and fourth ones of said modules, said first and second PLA circuits being programmed to produce outputs on said pins according to the following Boolean equations: ______________________________________ FIRST PLA CIRCUIT: FIRST SET: Output 1 = /1+/2+/3*/4*/5*/6; Output 2 = /1+/2+/3*/4*/5*/6*7; +3*/4*/5*/6; +/3*4*/5*/6*/7; Output 3 = /1+/2+3*/4*/5*/6*7; +/3*4*/5*/6*7; and, Output 4 = /1+/2+4*/5*/6*7; SECOND SET: Output 1 = /1+/2+/4*/5*/6*/7; +/3*/4*5*/6*/7; Output 2 = /1+/2+4*/5*/6*/7 +/4*5*/6*7; Output 3 = /1+/2+3*/4*5*/6*7 +/3*4*5*/6*7; and, Output 4 = /1+/2+4*5*/6*7; SECOND PLA CIRCUIT: FIRST SET: Output 1 = /1+/2+/3*/4*5*/6*/7+/3*/4*/5*6*7; Output 2 = /1+/2+3*/4*5*/6*/7+/3*4*5*/6*/7; +/4*/5*6*7; Output 3 = /1+/2+3*/4*/5*6*7+/3*4*/5*6*7; Output 4 /1+/2+4*/5*6*7; SECOND SET: Output 1 = /1+/2+/4*5*/6*/7+/3*/4*5*6*7; Output 2 = /1+/2+4*5*/6*/7+/4*5*6*7; Output 3 = /1+/2+3*/4*5*6*7+/3*4*5*6*7; and, Output 4 = /1+/2+4*5*6*7; ______________________________________ wherein the symbols +, * and / have the following meanings: +=OR function; *=AND function; and, /=the designated signal is low or a binary ZERO.

Claim 17

The memory subsystem of claim 10 wherein said input control signal when in a first state conditions said control means and said selector means to condition in turn said group of blocks of each one of said number of modules to read out said words in tandem from each one of said modules.

Claim 18

The memory subsystem of claim 10 wherein said input control signal when in a second state conditions said control means and said selector means to condition in turn said group of blocks of a different pair of adjacent modules to read out said words in tandem from said different pair of said adjacent modules.

Claim 19

The memory subsystem of claim 10 wherein said selector means includes a plurality of groups of selector circuits, each selector circuit of each group being coupled to a number of said plurality of blocks of chips of a different one of said number of modules, to said timing means and to receive said least significant bit of said address and said input control signal, said input control signal when in a first state indicating a common module configuration causing first and second ones of each group of selector circuits in succession to apply said timing signals to said number of said plurality of blocks of chips of a different one of said number of modules for read out of a plurality of words from a different one of said number of modules.

Claim 20

The memory subsystem of claim 17 wherein each of said number of modules of said common module configuration at least has twice as many word blocks as said number of modules when organized in an adjacent module configuration.

Claim 21

The memory subsystem of claim 17 wherein each of said selector circuits of each group are connected in common to said plurality of blocks of chips, said input control signal when in a second state indicating an adjacent module configuration conditioning only a predetermined one of said selector circuits of each group in sucession to apply said timing signals to said number of said plurality of blocks of chips for read out of said plurality of words from adjacent modules.