Method of producing an EPROM with a trench insulating layer

Claim 1

A method of producing an erasable-programmable read only memory (EPROM), comprising the steps of: (a) forming a field insulating layer defining a device formation region, on a semiconductor substrate, the portion of the substrate under the field insulating layer being of a first conductivity type; (b) forming a gate insulating layer on said device formation region; (c) forming a first conductor layer on said field and gate insulating layers; (d) forming a trench extending through said first conductor layer and said field insulating layer and into said semiconductor substrate; (e) filling said trench with an insulator; (f) forming a first interlaminar insulating layer covering said first conductor layer; (g) forming a second conductor layer on said first interlaminar insulating layer; (h) selectively etching said second conductor layer, said first interlaminar insulating layer, and said first conductor layer to form a floating gate and a control gate; (i) ion-implanting impurity ions in said semiconductor substrate, using said control gate formed in step (b) as a mask, to form a source region and a drain region, each of a second conductivity type opposite to the first conductivity type; (j) forming a second interlaminar insulating layer on said second conductor layer; and (k) forming a bit line traversing said floating gate and said control gate, on said second insulating layer.

Claim 2

A method of producing an erasable-programmable read only memory (EPROM), comprising the steps of: (a) forming a field insulating layer defining a device formation region, on a semiconductor substrate, the portion of the substrate under the field insulating layer being of a first conductivity type; (b) forming a gate insulating layer on said device formation region; (c) forming a first conductor layer on said field and gate insulating layers; (d) forming a trench extending through said first conductor layer and said field insulating layer and into said semiconductor substrate; (e) filling said trench with an insulator; (f) forming a first interlaminar insulating layer covering said first conductor layer; (g) forming a second conductor layer on said first interlaminar insulating layer; (h) selectively etching said second conductor layer, said first interlaminar insulating layer, and said first conductor layer to form a floating gate and a control gate; (i) ion-implanting impurity ions in said semiconductor substrate, using said control gate formed in step (b) as a mask, to form a source region and a drain region, each of a second conductivity type opposite to the first conductivity type; (j) forming a second interlaminar insulating layer on said second conductor layer; and (k) forming a bit line traversing said floating gate and said control gate, on said second insulating layer.