EP0428857A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Eeprom with trench-isolated bitlines
Assignee: Texas Instruments Inc
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Filing: 1990-10-10
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Granted: —
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Expires: 2010-10-10
Abstract
Abstract An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using a floating-gate transistor (10) with or without a split gate. The floating-gate transistor (10) may have a self-aligned tunnel window (26) or sublithographic dimension positioned on the opposite side of the source (11) from the channel and drain (12), in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines (17, 19) and source/drain regions (11,12) are buried beneath relatively thick silicon oxide (24a, 24b, 24c) and the floating gate (13) extends over the thick silicon oxide. Programming and erasing are accomplished by causing electrons to tunnel through the oxide in the tunnel window. The tunnel window has a thinner dielectric than the remainder of the oxides under the floating gate to allow Fowler-Nordheim tunneling. Trenches and ditches (27, 28) are used for electrical isolation between individual memory cells, allowing an increase in cell density.
Inventors
- 👤 Manzur Gill
- 👤 Sebastiano D'arrigo
- 👤 David J. Mcelroy
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 12:22
CPC Classifications
H; H10; H10B; H10B41/00; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
291 words
A nonvolatile memory array, comprising: first and second thermal oxide regions overlying source column lines formed in a face of a semiconductor body, said source column lines being doped regions of conductivity-type opposite that of the underlying material of said body, and said source column lines including sources of individual memory cells; third thermal oxide regions overlying drain column lines formed in said face of said semiconductor body parallel to and space from said source column lines, said drain column lines being doped regions of conductivity-type opposite that of the underlying material of said body, and said drain column lines including drains of said individual memory cells; each said source and each said drain of each said individual memory cell being spaced from each other on said face by a channel area, each said memory cell having a floating gate layer over at least a part of said channel area and extending onto at least said first and second thermal oxide regions, said floating gate layer being separated from said channel area by a gate insulator; and each said memory cell having a control gate extending along said face over said floating gate layer, said control gate being separated from said floating gate layer by an insulator layer; wherein a column of cells is separated from a first adjacent column of cells by a trench extending through said first thermal oxide region and through said source column region, and said column of cells is separated from a second adjacent column of cells by a trench extending through said through said third thermal oxide region and through said drain column region; and wherein each said cell has a tunnel area between said first thermal oxide region and said second thermal oxide region.
Claim 2
Dependent Claim
291 words
A nonvolatile memory array, comprising: first and second thermal oxide regions overlying source column lines formed in a face of a semiconductor body, said source column lines being doped regions of conductivity-type opposite that of the underlying material of said body, and said source column lines including sources of individual memory cells; third thermal oxide regions overlying drain column lines formed in said face of said semiconductor body parallel to and space from said source column lines, said drain column lines being doped regions of conductivity-type opposite that of the underlying material of said body, and said drain column lines including drains of said individual memory cells; each said source and each said drain of each said individual memory cell being spaced from each other on said face by a channel area, each said memory cell having a floating gate layer over at least a part of said channel area and extending onto at least said first and second thermal oxide regions, said floating gate layer being separated from said channel area by a gate insulator; and each said memory cell having a control gate extending along said face over said floating gate layer, said control gate being separated from said floating gate layer by an insulator layer; wherein a column of cells is separated from a first adjacent column of cells by a trench extending through said first thermal oxide region and through said source column region, and said column of cells is separated from a second adjacent column of cells by a trench extending through said through said third thermal oxide region and through said drain column region; and wherein each said cell has a tunnel area between said first thermal oxide region and said second thermal oxide region.
Claim 3
Dependent Claim
45 words
An array according to Claim 1, wherein a channel region of a cell in a row is separated from a channel region of a cell in an adjacent row by a ditch extending through said floating gate layer into said face of said semiconductor body.
Claim 4
Dependent Claim
71 words
An array according to Claim 1, wherein a channel region of a cell in a row is separated from a channel region of a cell in an adjacent row by a ditch extending through said floating gate layer into said face of said semiconductor body, wherein the bottom of said ditch includes a region doped with an impurity of the same conductivity-type as that of said face of said semiconductor body.
Claim 5
Dependent Claim
43 words
An array according to Claim 1, wherein a channel region of a cell in a row is separated from a channel region of a cell in an adjacent row by a LOCOS field oxide region formed in said face of said semiconductor body.
Claim 6
Dependent Claim
21 words
An array according to Claim 1, wherein said semiconductor body is silicon, and said source and drain regions are N+ type.
Claim 7
Dependent Claim
20 words
An array according to Claim 1, wherein said floating gate layers and said control gates are doped polycrystalline silicon layers.
Claim 8
Dependent Claim
17 words
An array according to Claim 1, wherein said thermal oxide regions are thicker than said gate insulator.
Claim 9
Dependent Claim
31 words
An array according to Claim 1, wherein said control gates are part of elongated row lines extending along said face perpendicular to said source column lines and said drain column lines.
Claim 10
Dependent Claim
21 words
An array according to Claim 1, wherein edges of said control gates are aligned with edges of said floating gate layers.
Claim 11
Dependent Claim
26 words
An array according to Claim 1, wherein no contact is formed between said source or drain and overlying conductor layers in the vicinity of each cell.
Claim 12
Dependent Claim
18 words
An array according to Claim 1, wherein the width of said tunnel areas is adjustable by oxide etch.
Claim 13
Dependent Claim
12 words
An array according to Claim 1, wherein said tunnel areas are self-aligned.
Claim 14
Dependent Claim
33 words
An array according to Claim 1, wherein the bottom surface of said trenches includes a region doped with an impurity of the same conductivity-type as that of said face of said semiconductor body.
Claim 15
Dependent Claim
19 words
An array according to Claim 1, wherein at least one of said trenches is filled with an oxide material.
Claim 16
Independent Claim
375 words
A method for making a nonvolatile memory array including column lines in a face of a semiconductor body and including row lines on said face, comprising: forming a layer of photoresist to expcse first line areas on said face 1f said semiconductor body; selectively implanting an impurity of conductivity-type opposite that of said semiconductor body into said face to create first source column lines in said first line areas on said face; growing first thermal oxide regions over said first source column lines; patterning a layer of photoresist on said face to expose second line areas adjacent said first line areas and to expose third line areas spaced from and parallel to said second line areas; selectively implanting an impurity of said opposite conductivity-type into said face to create second source column lines in said second line areas and to create drain column lines in said third line areas on said face; growing second and third thermal oxide regions over said second source column lines and said drain column lines; growing a gate oxide coating on said face over areas between said second source column lines and said drain column lines to a first thickness less than the thickness of said second and third thermal oxide regions; opening window areas between said first and second thermal oxide regions and regrowing gate oxides in said windows to a second thickness thinner than said first thickness to thereby provide tunnel windows; applying a first conductive layer on said face and patterning said first conductive layer to leave floating gate layers over channel areas between said second source column line and said drain column line, said conductive layer overlapping said first, second and third thermal oxide regions; forming trenches extending through said first conductive layer, said first thermal oxide regions and said first source column lines and forming trenches extending through said first conductive layer, said third thermal oxide regions and said drain column lines; applying a second conductive layer on said face overlying and insulated from said first conductive layer; and patterning and etching said second conductive layer and said first conductive layer to form floating gates and to form row lines perpendicular to said column lines, said row lines including control gates overlying said floating gates.
Claim 17
Independent Claim
375 words
A method for making a nonvolatile memory array including column lines in a face of a semiconductor body and including row lines on said face, comprising: forming a layer of photoresist to expcse first line areas on said face 1f said semiconductor body; selectively implanting an impurity of conductivity-type opposite that of said semiconductor body into said face to create first source column lines in said first line areas on said face; growing first thermal oxide regions over said first source column lines; patterning a layer of photoresist on said face to expose second line areas adjacent said first line areas and to expose third line areas spaced from and parallel to said second line areas; selectively implanting an impurity of said opposite conductivity-type into said face to create second source column lines in said second line areas and to create drain column lines in said third line areas on said face; growing second and third thermal oxide regions over said second source column lines and said drain column lines; growing a gate oxide coating on said face over areas between said second source column lines and said drain column lines to a first thickness less than the thickness of said second and third thermal oxide regions; opening window areas between said first and second thermal oxide regions and regrowing gate oxides in said windows to a second thickness thinner than said first thickness to thereby provide tunnel windows; applying a first conductive layer on said face and patterning said first conductive layer to leave floating gate layers over channel areas between said second source column line and said drain column line, said conductive layer overlapping said first, second and third thermal oxide regions; forming trenches extending through said first conductive layer, said first thermal oxide regions and said first source column lines and forming trenches extending through said first conductive layer, said third thermal oxide regions and said drain column lines; applying a second conductive layer on said face overlying and insulated from said first conductive layer; and patterning and etching said second conductive layer and said first conductive layer to form floating gates and to form row lines perpendicular to said column lines, said row lines including control gates overlying said floating gates.
Claim 18
Dependent Claim
41 words
A method according to Claim 15, wherein ditches are formed between said second thermal oxide region and said third thermal oxide region and between said row lines and wherein said ditches extend through said first conductive layer and said gate oxide.
Claim 19
Dependent Claim
66 words
A method according to Claim 15, wherein ditches are formed between said second thermal oxide region and said third thermal oxide region and between said row lines and wherein said ditches extend through said first conductive layer and said gate oxide and wherein a region at the bottom of said ditch is doped with an impurity of the same conductivity-type as that of said semiconductor body.
Claim 20
Dependent Claim
53 words
A method according to Claim 15, wherein LOCOS field oxide regions are formed in said semiconductor body between said second thermal oxide region and said third thermal oxide region and between said row lines and wherein said LOCOS regions are formed prior to forming said photoresist layer to expose said first line areas.
Claim 21
Dependent Claim
21 words
A method according to Claim 15, wherein said semiconductor body is P-type silicon and said impurity of opposite conductivity-type is N-type.
Claim 22
Dependent Claim
17 words
A method according to Claim 15, wherein said first and second conductive layers are doped polycrystalline silicon.
Claim 23
Dependent Claim
27 words
A method according to Claim 15, wherein an impurity of said opposite conductivity-type is implanted in said tunnel windows after regrowing said gate oxides in said windows.
Claim 24
Independent Claim
391 words
A method for making a nonvolatile memory array including column lines in a face of a semiconductor body and including row lines on said face, comprising: forming a layer of photoresist to expose first line areas and third line areas on said face of said semiconductor body, said third line areas parallel to and spaced from said first line areas; selectively implanting an impurity of conductivity-type opposite that of said semiconductor body into said face to create first source column lines in said first line areas on said face and to create drain column lines in said third line areas on said face of said semiconductor body; growing first thermal oxide regions over said first source column lines and third thermal oxide regions over said drain column lines; patterning a layer of photoresist on said face to expose second line areas adjacent said first line areas; selectively implanting an impurity of said opposite conductivity-type into said face to create second source column lines in said second line areas; growing second thermal oxide regions over said second source column lines; growing a gate oxide coating on said face over areas between said second source column lines and said drain column lines to a first thickness less than the thickness of said second oxide regions; opening window areas between said first and second thermal oxide regions and regrowing gate oxides in said windows to a second thickness thinner than said first thickness to thereby provide tunnel windows; applying a first conductive layer and an interlevel insulation layer on said face and patterning said first conductive layer and said interlevel insulation layer to leave floating gate layers over at least a part of each channel area between said second source column lines and said drain column lines, said floating gate layers overlapping at least said first and second thermal oxide regions; forming trenches extending through said first thermal oxide regions and said first source column lines and forming trenches extending through said third thermal oxide regions and said drain column lines; applying a second conductive layer on said face overlying and insulated from said first conductive layer; and patterning and etching said second conductive layer and said first conductive layer to form floating gates and to form row lines perpendicular to said column lines, said row lines including control gates overlying said floating gates.
Claim 25
Independent Claim
391 words
A method for making a nonvolatile memory array including column lines in a face of a semiconductor body and including row lines on said face, comprising: forming a layer of photoresist to expose first line areas and third line areas on said face of said semiconductor body, said third line areas parallel to and spaced from said first line areas; selectively implanting an impurity of conductivity-type opposite that of said semiconductor body into said face to create first source column lines in said first line areas on said face and to create drain column lines in said third line areas on said face of said semiconductor body; growing first thermal oxide regions over said first source column lines and third thermal oxide regions over said drain column lines; patterning a layer of photoresist on said face to expose second line areas adjacent said first line areas; selectively implanting an impurity of said opposite conductivity-type into said face to create second source column lines in said second line areas; growing second thermal oxide regions over said second source column lines; growing a gate oxide coating on said face over areas between said second source column lines and said drain column lines to a first thickness less than the thickness of said second oxide regions; opening window areas between said first and second thermal oxide regions and regrowing gate oxides in said windows to a second thickness thinner than said first thickness to thereby provide tunnel windows; applying a first conductive layer and an interlevel insulation layer on said face and patterning said first conductive layer and said interlevel insulation layer to leave floating gate layers over at least a part of each channel area between said second source column lines and said drain column lines, said floating gate layers overlapping at least said first and second thermal oxide regions; forming trenches extending through said first thermal oxide regions and said first source column lines and forming trenches extending through said third thermal oxide regions and said drain column lines; applying a second conductive layer on said face overlying and insulated from said first conductive layer; and patterning and etching said second conductive layer and said first conductive layer to form floating gates and to form row lines perpendicular to said column lines, said row lines including control gates overlying said floating gates.
Claim 26
Dependent Claim
41 words
A method according to Claim 22, wherein ditches are formed between said second thermal oxide regions and said third thermal oxide regions and between said row lines and wherein said ditches extend through said first conductive layer and said gate oxide.
Claim 27
Dependent Claim
66 words
A method according to Claim 22, wherein ditches are formed between said second thermal oxide regions and said third thermal oxide regions and between said row lines and wherein said ditches extend through said first conductive layer and said gate oxide and wherein a region at the bottom of said ditch is doped with an impurity of the same conductivity-type as that of said semiconductor bcdy.
Claim 28
Dependent Claim
53 words
A method according to Claim 22, wherein LOCOS field oxide regions are formed in said semiconductor body between said second thermal oxide regions and said third thermal oxide regions and between said row lines and wherein said LOCOS regions are formed prior to forming said photoresist layer to expose said first line areas.
Claim 29
Dependent Claim
21 words
A method according to Claim 22, wherein said semiconductor body is P-type silicon and said impurity of opposite conductivity-type is N-type.
Claim 30
Dependent Claim
17 words
A method according to Claim 22, wherein said first and second conductive layers are doped polycrystalline silicon.
Claim 31
Dependent Claim
27 words
A method according to Claim 22, wherein an impurity of said opposite conductivity-type is implanted in said tunnel windows after regrowing said gate oxides in said windows.
Claim 32
Dependent Claim
21 words
A method according to Claim 22, wherein said trenches are formed, then filled with oxide, prior to patterning said photoresist layer.
References Cited (Backward Citations)
No citation records indexed.
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