Patent US5729440A successfully refreshed from Google Patents.
US5729440A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Solder hierarchy for chip attachment to substrates
Assignee: International Business Machines Corp
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Filing: 1997-01-16
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Granted: 1998-03-17
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Expires: 2017-01-16
Abstract
Abstract The method for soldering a chip to a substrate to form a module and then soldering the module to a circuit board includes selecting a three level hierarchy of solders by the temperature required to melt. By this method, a module can be soldered to and de-soldered from a circuit board without affecting adversely the solder between the chip and the substrate. The package formed by this method is free of faults that are caused frequently during both manufacture and service.
Inventors
- 👤 Miguel Angel Jimarez
- 👤 Amit Kumar Sarkhel
- 👤 Lawrence Harold White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:52
CPC Classifications
B; B23; B23K; B23K1/00; B23K1/0008; B23K1/0016; B23K35/00; B23K35/22; B23K35/24; B23K35/26; B23K35/262; B23K35/268; H; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/346; H10; H10W; H10W74/00; H10W74/01; H10W74/012; H10W74/10; H10W74/15; B23K2101/00; B23K2101/36; B23K2101/40; B23K35/001; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/09372; H05K2201/094; H05K3/341; H05K3/3431; H10W72/00; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/20; H10W72/251; H10W72/252; H10W72/851; H10W72/853; H10W72/856; H10W90/00; H10W90/701; H10W90/731; H10W90/734; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
119 words
An organic chip package, comprising: a substrate formed of at least one layer of organic dielectric material, with an electrical circuit of a predetermined arrangement with points for connecting either to an external power source or to an external circuit; a chip with connection points of first solder material with a predetermined melting temperature of at least 300 degrees C. and formed of either 95% Pb and 5% Sn or 96.5% Pb and 3.5% Sn; and second solder material formed in the range of 2.0% to 3.5% Ag-98% to 96.5% Sn solder selected from a group of solders with a melting temperature in the range of 220 to 240 degrees C. attaching said first solder material to said substrate.
Claim 2
Dependent Claim
119 words
An organic chip package, comprising: a substrate formed of at least one layer of organic dielectric material, with an electrical circuit of a predetermined arrangement with points for connecting either to an external power source or to an external circuit; a chip with connection points of first solder material with a predetermined melting temperature of at least 300 degrees C. and formed of either 95% Pb and 5% Sn or 96.5% Pb and 3.5% Sn; and second solder material formed in the range of 2.0% to 3.5% Ag-98% to 96.5% Sn solder selected from a group of solders with a melting temperature in the range of 220 to 240 degrees C. attaching said first solder material to said substrate.
Claim 3
Dependent Claim
28 words
An organic chip package as described by claim 1 including a carrier formed of a predetermined organic material, and said substrate being attached by a third solder material.
Claim 4
Dependent Claim
27 words
An organic chip package as defined by claim 2 wherein said first solder material has a melting temperature in the order of at least 300 degrees C.
Claim 5
Dependent Claim
28 words
An organic chip package as defined by claim 3 wherein said second solder material has a melting temperature of intermediate that of said first and third solder materials.
Claim 6
Dependent Claim
96 words
An organic chip package as defined by claim 1 wherein said organic chip package is assembled with a hierarchy of solders by their melting temperatures, a chip having solder bumps of a first temperature, said solder bumps being attached to said electrical circuit by said second solder material having a second temperature lower than said first temperature, and said substrate being attached to a circuit board by a solder material of a third temperature lower than said second temperature, so that said package can be detached from said circuit board without affecting adversely other solder attachments.
References Cited (Backward Citations)
JPS6214433A
Cited
US5090609A
Cited
US5007163A
Cited
US5147084A
Cited
US5154341A
Cited
US5261593A
Cited
US5234149A
Cited
US5275330A
Cited
US5439162A
Cited
US5535526A
Cited
US5611481A
Cited
US5551627A
Cited
US5655703A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-16 | 2001-09-15 | 2002-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-16 | 2005-09-15 | 2006-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-16 | 2009-09-15 | 2010-03-17 | $7700.00 | Window Closed / Lapsed |