Patent US5728628A successfully refreshed from Google Patents.
US5728628A
Expired / Lapsed
US
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Two-step metal etch process for selective gap fill of submicron inter-connects and structure for same
Assignee: Texas Instruments Inc
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Filing: 1996-02-26
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Granted: 1998-03-17
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Expires: 2016-02-26
Abstract
Abstract A semiconductor device and method having a low-permittivity material between closely-spaced leads in order to decrease unwanted capacitance, while having a more structurally strong dielectric between widely-spaced leads where capacitance is not as critical. Metal layer 14 is deposited on a substrate 12 of a semiconductor wafer 10, where the metal layer 14 has a first portion 15 and a second portion 17. Widely-spaced leads 16 are formed in the first portion 15 of the metal layer 14, and a first structural dielectric layer 26 is deposited on at least the widely-spaced leads. Closely-spaced leads 18 are formed in the second portion 17 of the metal layer 14, and low-permittivity material 34 is deposited between closely-spaced leads 18. A second structural dielectric layer 36 is deposited on at least low-permittivity material 34 and closely-spaced leads 18. An advantage of the invention includes improved structural strength by placing structurally weak low-permittivity material only where needed, in areas having closely-spaced leads.
Inventors
- 👤 Robert H. Havemann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:33
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/48; H10W20/01; H10W20/071; H10W20/074; H10W20/076; H10W20/077; H10W20/098; H10W20/41; H10W20/43; H10W20/495
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
163 words
A method for patterning a metal layer on a semiconductor wafer having a substrate, comprising the steps of: depositing a metal layer on said substrate, said metal layer having a first portion and a second portion; then forming widely-spaced leads in said first portion of said metal layer, said widely-spaced leads having leads spaced apart by more than the thickness of said metal layer; then depositing a first structural dielectric layer on at least said widely-spaced leads and forming at least portions of closely-spaced leads in said second portion of said metal layer, said closely-spaced leads having leads spaced apart less than or equal to the thickness of said metal layer; then depositing a low-permittivity material between at least said closely-spaced leads, said low-permittivity material providing a dielectric constant of less than 3 in a region between at least two of said closely-spaced metal leads; and then depositing a second structural dielectric layer over at least said low-permittivity material and said closely-spaced leads.
Claim 2
Independent Claim
163 words
A method for patterning a metal layer on a semiconductor wafer having a substrate, comprising the steps of: depositing a metal layer on said substrate, said metal layer having a first portion and a second portion; then forming widely-spaced leads in said first portion of said metal layer, said widely-spaced leads having leads spaced apart by more than the thickness of said metal layer; then depositing a first structural dielectric layer on at least said widely-spaced leads and forming at least portions of closely-spaced leads in said second portion of said metal layer, said closely-spaced leads having leads spaced apart less than or equal to the thickness of said metal layer; then depositing a low-permittivity material between at least said closely-spaced leads, said low-permittivity material providing a dielectric constant of less than 3 in a region between at least two of said closely-spaced metal leads; and then depositing a second structural dielectric layer over at least said low-permittivity material and said closely-spaced leads.
Claim 3
Dependent Claim
38 words
The method of claim 1 wherein said forming at least portions of closely-spaced leads in said second portion of said metal layer is performed before said depositing a first structural dielectric layer on at least said widely-spaced leads.
Claim 4
Dependent Claim
23 words
The method of claim 1 wherein the step of forming said closely-spaced leads precedes the step of depositing said first structural dielectric layer.
Claim 5
Dependent Claim
19 words
The method of claim 1 wherein all of said closely-spaced leads are formed during said forming closely-spaced leads step.
Claim 6
Dependent Claim
26 words
The method of claim 1 and further comprising the step of planarizing said first structural dielectric layer, after said depositing a first structural dielectric layer step.
Claim 7
Dependent Claim
64 words
The method of claim 1 and further comprising, after said step of depositing a metal layer, the sequential steps of: depositing a etch-stopping dielectric layer on said metal layer; patterning said etch-stopping dielectric layer; and covering said second portion of said metal layer; and further comprising, before said step of forming closely-spaced leads, the step of: uncovering said second portion of said metal layer.
Claim 8
Dependent Claim
112 words
The method of claim 1 further comprising, after said step of depositing a metal layer, the sequential steps of: covering said second portion of said metal layer; and patterning said first portion of said metal layer; further comprising, after said step of forming widely-spaced leads, the step of: uncovering said second portion of said metal layer; further comprising, after said step of depositing a first structural dielectric layer, the sequential steps of: covering said first portion of said metal layer; and patterning said second portion of said metal layer; and further comprising, after said step of forming portions of closely-spaced leads, the step of: uncovering said first portion of said metal layer.
Claim 9
Independent Claim
200 words
A method for patterning a metal layer on a semiconductor wafer having a substrate, comprising the steps of: depositing a metal layer on a substrate, said metal layer having a first portion and a second portion; depositing an etch-stopping dielectric layer on said metal layer; depositing a resist layer on said etch-stopping dielectric layer; patterning said resist layer to form a conductor pattern; etching said etch-stopping dielectric layer and said metal to form metal leads, said metal leads having widely-spaced leads in said first portion of said metal layer wherein said widely-spaced leads have leads spaced apart by more than the thickness of said metal layer, said metal leads having closely-spaced leads in said second portion of said metal layer wherein said closely-spaced leads have leads spaced apart less than or equal to the thickness of said metal layer; depositing a first structural dielectric layer on at least said widely-spaced leads; depositing a low-permittivity material between at least said closely-spaced leads, said low-permittivity material providing a dielectric constant of less than 3 in a region between at least two of said metal leads; and depositing a second structural dielectric layer on at least said low-permittivity material and said closely-spaced leads.
Claim 10
Independent Claim
200 words
A method for patterning a metal layer on a semiconductor wafer having a substrate, comprising the steps of: depositing a metal layer on a substrate, said metal layer having a first portion and a second portion; depositing an etch-stopping dielectric layer on said metal layer; depositing a resist layer on said etch-stopping dielectric layer; patterning said resist layer to form a conductor pattern; etching said etch-stopping dielectric layer and said metal to form metal leads, said metal leads having widely-spaced leads in said first portion of said metal layer wherein said widely-spaced leads have leads spaced apart by more than the thickness of said metal layer, said metal leads having closely-spaced leads in said second portion of said metal layer wherein said closely-spaced leads have leads spaced apart less than or equal to the thickness of said metal layer; depositing a first structural dielectric layer on at least said widely-spaced leads; depositing a low-permittivity material between at least said closely-spaced leads, said low-permittivity material providing a dielectric constant of less than 3 in a region between at least two of said metal leads; and depositing a second structural dielectric layer on at least said low-permittivity material and said closely-spaced leads.
Claim 11
Dependent Claim
23 words
The method of claim 8 wherein said low-permittivity material is also deposited between said etch-stopping dielectric layer in areas adjacent said closely-spaced leads.
Claim 12
Dependent Claim
26 words
The method of claim 8 and further comprising the step of planarizing said first structural dielectric layer, after said depositing a first structural dielectric layer step.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-16 | 2001-09-15 | 2002-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-16 | 2005-09-15 | 2006-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-16 | 2009-09-15 | 2010-03-17 | $7700.00 | Window Closed / Lapsed |