US5726475A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having different impurity concentration wells
Assignee: Toshiba Corp
•
Filing: 1994-09-16
•
Granted: 1998-03-10
•
Expires: 2014-09-16
Abstract
Abstract A semiconductor device comprises an N-type semiconductor substrate, a first P-type well formed in the semiconductor substrate, a second P-type well formed adjacent to the first P-type well in the semiconductor substrate, the surface impurity concentration of the second P-type well being set lower than that of the first P-type well, a DRAM memory cell structure formed in the first P-type well, and an MOS transistor structure formed in the second P-type well to function in combination with the memory cell structure.
Inventors
- 👤 Shizuo Sawada
- 👤 Syuso Fujii
- 👤 Masaki Ogihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:57
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/31; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0156; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
140 words
A semiconductor memory comprising: a P-type substrate; an N-type region formed in said substrate; a first P-type region formed in said N-type region; a memory cell structure formed in said first P-type region and including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; a region containing a transistor structure formed in said substrate adjacent to said memory cell structure, said transistor structure including transistor source and drain regions, and a transistor gate electrode; a second P-type region formed in said substrate, said second P-type region being located between said memory cell structure and said transistor structure, wherein a surface impurity concentration of said first P-type region is higher than surface impurity concentrations of said substrate and said second P-type region; and means for supplying a predetermined potential to said N-type region.
Claim 2
Dependent Claim
140 words
A semiconductor memory comprising: a P-type substrate; an N-type region formed in said substrate; a first P-type region formed in said N-type region; a memory cell structure formed in said first P-type region and including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; a region containing a transistor structure formed in said substrate adjacent to said memory cell structure, said transistor structure including transistor source and drain regions, and a transistor gate electrode; a second P-type region formed in said substrate, said second P-type region being located between said memory cell structure and said transistor structure, wherein a surface impurity concentration of said first P-type region is higher than surface impurity concentrations of said substrate and said second P-type region; and means for supplying a predetermined potential to said N-type region.
Claim 3
Dependent Claim
140 words
A semiconductor memory comprising: an N-type substrate; a P-type region formed in said substrate; a first N-type region formed in said P-type region; a memory cell structure formed in said N-type region and including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; a region containing a transistor structure formed in said substrate adjacent to said memory cell structure, said transistor structure including transistor source and drain regions, and a transistor gate electrode; a second N-type region formed in said substrate, said second N-type region being located between said memory cell structure and said transistor structure, wherein a surface impurity concentration of said first N-type region is higher than surface impurity concentrations of said substrate and said second N-type region: and means for supplying a predetermined potential to said first N-type region.
Claim 4
Dependent Claim
140 words
A semiconductor memory comprising: an N-type substrate; a P-type region formed in said substrate; a first N-type region formed in said P-type region; a memory cell structure formed in said N-type region and including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; a region containing a transistor structure formed in said substrate adjacent to said memory cell structure, said transistor structure including transistor source and drain regions, and a transistor gate electrode; a second N-type region formed in said substrate, said second N-type region being located between said memory cell structure and said transistor structure, wherein a surface impurity concentration of said first N-type region is higher than surface impurity concentrations of said substrate and said second N-type region: and means for supplying a predetermined potential to said first N-type region.
Claim 5
Dependent Claim
153 words
A semiconductor memory comprising: a P-type substrate; a well region formed in said substrate; a P-type memory cell region, containing a memory cell structure, formed in a first part of said well region, said memory cell structure including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; a P-type transistor structure formed in a second part of said well region and including transistor source and drain regions, and a transistor gate electrode; an N-type region formed in a third part of said well region, said N-type region being located between said memory cell region and said P-type transistor structure, wherein a surface impurity concentration of said memory cell region is higher than surface impurity concentrations of said P-type substrate and said P-type transistor structure; and means for supplying a predetermined potential to both said memory cell region and said third part of said well region.
Claim 6
Dependent Claim
153 words
A semiconductor memory comprising: a P-type substrate; a well region formed in said substrate; a P-type memory cell region, containing a memory cell structure, formed in a first part of said well region, said memory cell structure including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; a P-type transistor structure formed in a second part of said well region and including transistor source and drain regions, and a transistor gate electrode; an N-type region formed in a third part of said well region, said N-type region being located between said memory cell region and said P-type transistor structure, wherein a surface impurity concentration of said memory cell region is higher than surface impurity concentrations of said P-type substrate and said P-type transistor structure; and means for supplying a predetermined potential to both said memory cell region and said third part of said well region.
Claim 7
Dependent Claim
129 words
A semiconductor memory comprising: a P-type substrate; a P-type memory cell region containing a memory cell structure, said memory cell structure including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; an N-type region containing a transistor structure formed in said substrate, said transistor structure including transistor source and drain regions, and a transistor gate electrode; a P-type region formed in said substrate, said P-type region being located between said P-type memory cell region and said transistor structure, wherein a surface impurity concentration of said P-type region is higher than surface impurity concentrations of said P-type substrate and said P-type memory cell region; and means for supplying a predetermined potential to both said P-type memory cell region and said P-type region.
Claim 8
Dependent Claim
129 words
A semiconductor memory comprising: a P-type substrate; a P-type memory cell region containing a memory cell structure, said memory cell structure including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; an N-type region containing a transistor structure formed in said substrate, said transistor structure including transistor source and drain regions, and a transistor gate electrode; a P-type region formed in said substrate, said P-type region being located between said P-type memory cell region and said transistor structure, wherein a surface impurity concentration of said P-type region is higher than surface impurity concentrations of said P-type substrate and said P-type memory cell region; and means for supplying a predetermined potential to both said P-type memory cell region and said P-type region.
Claim 9
Dependent Claim
130 words
A semiconductor memory comprising: a substrate; a well region formed in said substrate; a P-type memory cell region, containing a trench cell type memory cell structure, formed in a first part of said well region, said memory cell structure including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; a P-type transistor structure formed in a second part of said well region and including transistor source and drain regions, and a transistor gate electrode; and an N-type region formed in a third part of said well region, said N-type region being located between said memory cell region and said transistor structure, wherein a surface impurity concentration of said P-type memory cell region is higher than a surface impurity concentration of said substrate.
Claim 10
Dependent Claim
130 words
A semiconductor memory comprising: a substrate; a well region formed in said substrate; a P-type memory cell region, containing a trench cell type memory cell structure, formed in a first part of said well region, said memory cell structure including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; a P-type transistor structure formed in a second part of said well region and including transistor source and drain regions, and a transistor gate electrode; and an N-type region formed in a third part of said well region, said N-type region being located between said memory cell region and said transistor structure, wherein a surface impurity concentration of said P-type memory cell region is higher than a surface impurity concentration of said substrate.
Claim 11
Dependent Claim
155 words
A semiconductor memory comprising: a P-type substrate; a well region formed in said substrate; a P-type memory cell region, containing a stacked trench cell type memory cell structure, formed in a first part of said well region, said memory cell structure comprising a trench formed by polysilicon and containing insulation film, memory cell source and drain regions, a memory cell gate electrode, and an elongated memory cell capacitor electrode, wherein said elongated memory cell capacitor electrode extends into said trench; a P-type transistor structure formed in a second part of said well region and including transistor source and drain regions, and a transistor gate electrode; and an N-type region formed in a third part of said well region, said N-type region being located between said P-type memory cell region and said transistor structure, wherein a surface impurity concentration of said P-type memory cell region is higher than a surface impurity concentration of said P-type substrate.
Claim 12
Dependent Claim
155 words
A semiconductor memory comprising: a P-type substrate; a well region formed in said substrate; a P-type memory cell region, containing a stacked trench cell type memory cell structure, formed in a first part of said well region, said memory cell structure comprising a trench formed by polysilicon and containing insulation film, memory cell source and drain regions, a memory cell gate electrode, and an elongated memory cell capacitor electrode, wherein said elongated memory cell capacitor electrode extends into said trench; a P-type transistor structure formed in a second part of said well region and including transistor source and drain regions, and a transistor gate electrode; and an N-type region formed in a third part of said well region, said N-type region being located between said P-type memory cell region and said transistor structure, wherein a surface impurity concentration of said P-type memory cell region is higher than a surface impurity concentration of said P-type substrate.
Claim 13
Dependent Claim
160 words
A semiconductor memory comprising: a P-type substrate; an N-type region formed in said substrate; a first P-type region formed in said N-type region; a memory cell structure formed in said first P-type region and including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; a region containing a transistor structure formed in said substrate adjacent to said memory cell structure, said transistor structure including transistor source and drain regions, and a transistor gate electrode; a second P-type region formed in said substrate and being located between said memory cell structure and said transistor structure, wherein a surface impurity concentration of said first P-type region is higher than surface impurity concentrations of said P-type substrate and said second P type region, and the surface impurity concentration of said second P-type region is higher than the surface impurity concentration of said P-type substrate; and means for supplying a predetermined potential to said N-type region.
Claim 14
Dependent Claim
160 words
A semiconductor memory comprising: a P-type substrate; an N-type region formed in said substrate; a first P-type region formed in said N-type region; a memory cell structure formed in said first P-type region and including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; a region containing a transistor structure formed in said substrate adjacent to said memory cell structure, said transistor structure including transistor source and drain regions, and a transistor gate electrode; a second P-type region formed in said substrate and being located between said memory cell structure and said transistor structure, wherein a surface impurity concentration of said first P-type region is higher than surface impurity concentrations of said P-type substrate and said second P type region, and the surface impurity concentration of said second P-type region is higher than the surface impurity concentration of said P-type substrate; and means for supplying a predetermined potential to said N-type region.
Claim 15
Dependent Claim
141 words
A semiconductor memory comprising: a P-type substrate; a first P-type region formed in said substrate; a memory cell structure formed in said first P-type region and including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; a region containing a transistor structure formed in said substrate adjacent to said memory cell structure, said transistor structure including transistor source and drain regions, and a transistor gate electrode; a second P-type region formed in an N-type region, said second P-type, region being located between said memory cell structure and said transistor structure, wherein a surface impurity concentration of said first P-type region is higher than surface impurity concentrations of said P-type substrate and said second P-type region; and means for supplying a predetermined potential to said transistor structure and said first and second P-type regions.
Claim 16
Dependent Claim
141 words
A semiconductor memory comprising: a P-type substrate; a first P-type region formed in said substrate; a memory cell structure formed in said first P-type region and including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; a region containing a transistor structure formed in said substrate adjacent to said memory cell structure, said transistor structure including transistor source and drain regions, and a transistor gate electrode; a second P-type region formed in an N-type region, said second P-type, region being located between said memory cell structure and said transistor structure, wherein a surface impurity concentration of said first P-type region is higher than surface impurity concentrations of said P-type substrate and said second P-type region; and means for supplying a predetermined potential to said transistor structure and said first and second P-type regions.
Claim 17
Dependent Claim
111 words
A semiconductor memory comprising: a P-type substrate; an N-type region formed in said substrate; a first P-type region formed in said N-type region; a memory cell structure formed in said first P type region and including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; and a second P-type region containing a transistor structure formed in said substrate adjacent to said memory cell structure, said transistor structure including transistor source and drain regions, and a transistor gate electrode, wherein a surface impurity concentration of said first P-type region is higher than surface impurity concentrations of said P-type substrate and said second P-type region.
Claim 18
Dependent Claim
111 words
A semiconductor memory comprising: a P-type substrate; an N-type region formed in said substrate; a first P-type region formed in said N-type region; a memory cell structure formed in said first P type region and including memory cell source and drain regions, a memory cell gate electrode, and a memory cell capacitor electrode; and a second P-type region containing a transistor structure formed in said substrate adjacent to said memory cell structure, said transistor structure including transistor source and drain regions, and a transistor gate electrode, wherein a surface impurity concentration of said first P-type region is higher than surface impurity concentrations of said P-type substrate and said second P-type region.
Claim 19
Dependent Claim
25 words
A semiconductor memory as recited in claim 9, further comprising means for supplying a predetermined potential to said N-type region and said first P-type region.
References Cited (Backward Citations)
US4233672A
Cited
JPS55160463A
Cited
US4413401A
Cited
US4642667A
Cited
JPS60200568A
Cited
EP0159824A2
Cited
US4672410A
Cited
JPS6197860A
Cited
JPS60143665A
Cited
US4673962A
Cited
US5079613A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-09 | 2001-09-08 | 2002-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-09 | 2005-09-08 | 2006-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-09 | 2009-09-08 | 2010-03-10 | $7700.00 | Window Closed / Lapsed |