Semiconductor memory device

Abstract

Abstract PURPOSE:To enhance the latchup withstanding property by providing a memory cell in a low specific resistance region, and forming a peripheral circuit element in a high specific resistance region, thereby preventing a memory cell for inducing minority carrier due to alpha-ray and impact ionization from erroneously operating. CONSTITUTION:A memory cell is formed in a well 9 of a low specific resistance in opposite conductivity to a substrate, and a peripheral circuit element is provided in a well 10 of a high specific resistance in opposite conductivity to a substrate. Thus, the memory cell has large P-N junction capacity in the well 9 of the low specific resistance and large storage capacity of memory cell. Thus, software error hardly occur due to alpha-ray, and the substrate of a parasitic PNPN transistor and the potential of the well are suppressed in variation in the same current amount as the well potential to cause a latchup withstand voltage to become high, thereby increasing the latchup current as the entire semiconductor memory. On the other hand, a peripheral circuit element is disposed in the well 10 having small P-N junction capacity. Thus high speed operation can be performed.

Inventors

• 👤 Shozo Nishimoto
• 👤 西本　昭三

Bibliographic Details