US5726089A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and method for fabricating the same
Assignee: NEC Electronics Corp
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Filing: 1995-11-27
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Granted: 1998-03-10
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Expires: 2015-11-27
Abstract
Abstract A method for fabricating a semiconductor device having a bonded wafer structure capable of reducing crystal defect in a power element forming region thereof is disclosed A recess is formed in a control circuit element forming region of a first n- silicon substrate, then filled with a silicon oxide film and subjected to grinding and polishing to provide a mirror-surface. An n- epitaxial layer is formed on the surface of a second n+ silicon substrate, then the surface of the epitaxial layer is coupled to the surfaces of the silicon oxide film and second circuit region of the first substrate and heat-treated to be bonded thereto.
Inventors
- 👤 Kensuke Okonogi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:06
CPC Classifications
H; H10; H10P; H10P10/00; H10P10/12; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10P90/1914; H10W10/011; H10W10/012; H10W10/014; H10W10/041; H10W10/13; H10W10/17; H10W10/40
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
219 words
A method for fabricating a semiconductor device having a bonded wafer including a first and a second silicon substrate of a first conductivity type and having a first circuit region in said first silicon substrate and a second circuit region in said first and second silicon substrates, said first silicon substrate having a resistivity higher than the resistivity of the second substrate, said method including steps of: forming a recess in said first circuit region of said first silicon substrate; forming an insulating layer within said recess, said insulating layer having an uppermost surface recessed within said recess; forming a polycrystalline silicon layer covering an entire surface including the surfaces of said insulating layer and said second region of said first silicon substrate; grinding and polishing at least said polycrystalline silicon layer to cause a surface of said polycrystalline silicon layer to be flush with the surface of said second circuit region of said first silicon substrate; forming an epitaxial layer on said second substrate; bonding the surfaces of said ground polycrystalline silicon layer and second circuit region of said first silicon substrate to the surface of said epitaxial layer, thereby to obtain said bonded wafer, in which only said polycrystalline silicon layer and the surface of said first substrate are bonded to said surface of said epitaxial layer.
Claim 2
Independent Claim
219 words
A method for fabricating a semiconductor device having a bonded wafer including a first and a second silicon substrate of a first conductivity type and having a first circuit region in said first silicon substrate and a second circuit region in said first and second silicon substrates, said first silicon substrate having a resistivity higher than the resistivity of the second substrate, said method including steps of: forming a recess in said first circuit region of said first silicon substrate; forming an insulating layer within said recess, said insulating layer having an uppermost surface recessed within said recess; forming a polycrystalline silicon layer covering an entire surface including the surfaces of said insulating layer and said second region of said first silicon substrate; grinding and polishing at least said polycrystalline silicon layer to cause a surface of said polycrystalline silicon layer to be flush with the surface of said second circuit region of said first silicon substrate; forming an epitaxial layer on said second substrate; bonding the surfaces of said ground polycrystalline silicon layer and second circuit region of said first silicon substrate to the surface of said epitaxial layer, thereby to obtain said bonded wafer, in which only said polycrystalline silicon layer and the surface of said first substrate are bonded to said surface of said epitaxial layer.
Claim 3
Dependent Claim
14 words
The method as defined in claim 1, wherein said recess has a flat bottom.
Claim 4
Dependent Claim
34 words
The method as defined in claim 1 wherein said first silicon substrate has a resistivity of 10 to 30 Ω-cm and said second substrate has a resistivity of 10 -3 to 2×10 -1 Ω-cm.
Claim 5
Dependent Claim
28 words
The method as defined in claim 1 further including a step of forming a plurality of isolation regions for separating said first circuit region after said bonding step.
Claim 6
Dependent Claim
85 words
The method as defined in claim 1, wherein said step of forming an insulating layer within said recess comprises the steps of: forming successively a silicon oxide film and a silicon nitride film on the surface of said first circuit region of said first silicon substrate except a bottom portion of said recess; forming an insulating layer in said bottom portion of said recess by using said silicon nitride film as a selective mask; and removing said silicon oxide film and said silicon nitride film.
Claim 7
Dependent Claim
23 words
The method as defined in claim 1, wherein said epitaxial layer has a resistivity equal to the resistivity of the first silicon substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-09 | 2001-09-08 | 2002-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-09 | 2005-09-08 | 2006-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-09 | 2009-09-08 | 2010-03-10 | $7700.00 | Window Closed / Lapsed |