US5374582A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Laminated substrate for semiconductor device and manufacturing method thereof
Assignee: NEC Electronics Corp
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Filing: 1994-04-28
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Granted: 1994-12-20
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Expires: 2014-04-28
Abstract
Abstract A method for fabricating a laminated substrate for a semiconductor device having a high voltage power device and a low voltage element formed in a region isolated from the power device with a P-N junction. The region for the low voltage element is formed on a buried layer of P type formed in the region of N type in which the power device is formed and surrounded by a isolating region of P type reaching the buried layer from the surface of the laminated substrate.
Inventors
- 👤 Kensuke Okonogi
- 👤 Hiroaki Kikuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:42
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10P10/00; H10P10/12; H10P10/128; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/10; H10W10/181; H10W10/30; Y; Y10; Y10S; Y10S148/00; Y10S148/012
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
200 words
A method for manufacturing a laminated substrate for a semiconductor device comprising the steps of: (a) preparing a first semiconductor substrate of a first conductivity type and a second semiconductor substrate of the first conductivity type, said first semiconductor substrate having a first main surface and a second main surface opposite to said first main surface and said second semiconductor substrate having a third main surface and a fourth main surface opposite to said third main surface; (b) forming a first region of a second conductivity type by selectively introducing impurities into said first main surface of said first semiconductor substrate; (c) forming an epitaxial layer of the first conductivity type on said third main surface of said second semiconductor substrate; (d) placing said first main surface of the first semiconductor substrate and a surface of said epitaxial layer in contact with each other and then heating said first and second semiconductor substrates to bond each other; (e) polishing said second main surface of said first semiconductor substrate to produce a polished surface; and (f) forming an isolating region of the second conductivity type reaching said first region by introducing impurities into said first semiconductor substrate from said polished surface.
Claim 2
Independent Claim
200 words
A method for manufacturing a laminated substrate for a semiconductor device comprising the steps of: (a) preparing a first semiconductor substrate of a first conductivity type and a second semiconductor substrate of the first conductivity type, said first semiconductor substrate having a first main surface and a second main surface opposite to said first main surface and said second semiconductor substrate having a third main surface and a fourth main surface opposite to said third main surface; (b) forming a first region of a second conductivity type by selectively introducing impurities into said first main surface of said first semiconductor substrate; (c) forming an epitaxial layer of the first conductivity type on said third main surface of said second semiconductor substrate; (d) placing said first main surface of the first semiconductor substrate and a surface of said epitaxial layer in contact with each other and then heating said first and second semiconductor substrates to bond each other; (e) polishing said second main surface of said first semiconductor substrate to produce a polished surface; and (f) forming an isolating region of the second conductivity type reaching said first region by introducing impurities into said first semiconductor substrate from said polished surface.
Claim 3
Dependent Claim
57 words
The method of claim 1, further comprising the steps of forming a groove reaching said buried layer in said isolating region, forming an insulating film on a surface of said groove, and forming polycrystalline silicon on a surface of said insulating film, said insulating film and said polycrystalline silicon cooperating to each other to fill said groove.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-19 | 1998-06-20 | 1998-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-19 | 2002-06-20 | 2002-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-19 | 2006-06-20 | 2006-12-20 | $7700.00 | Window Closed / Lapsed |