Integrated polysilicon diode contact for gain memory cells

Claim 2

An integrated polysilicon diode contact, comprising: a gate oxide layer deposited on a silicon substrate; a first highly doped layer having a dopant of a first type deposited on said gate oxide layer; a source region formed in a surface of said silicon substrate, wherein said source region has a dopant of the first type; a second highly doped layer having a dopant of a second different type deposited on said source region, said second highly doped layer being spaced from said gate oxide layer and said first highly doped layer; and a third lower doped layer having a dopant of the second type deposited on and interconnecting said first highly doped layer and said second highly doped layer, said third lower doped layer forming a p-n junction with said source region.

Claim 3

A diode contact as in claim 1, wherein said first highly doped layer is one of silicon and polysilicon.

Claim 4

A diode contact as in claim 2, wherein said first highly doped layer has a dopant concentration of about 5×10 19 cm -3 .

Claim 5

A diode contact as in claim 3, wherein said dopant of the first type is arsenic or phosphorus.

Claim 6

A diode contact as in claim 4, wherein said second highly doped layer is one of silicon and polysilicon.

Claim 7

A diode contact as in claim 5, wherein said second highly doped layer has a dopant concentration of about 1×10 20 cm -3 .

Claim 8

A diode contact as in claim 6, wherein said dopant of the second type is boron.

Claim 9

A diode contact as in claim 7, wherein said source region has a dopant concentration of about 5×10 20 cm -3 .

Claim 10

A diode contact as in claim 8, wherein said third lower doped layer is one of silicon and polysilicon.

Claim 11

A diode contact as in claim 9, wherein said third lower doped layer has a dopant concentration of about 5×10 20 cm -3 .

Claim 12

A diode contact as in claim 6, wherein said second highly doped layer has a thickness of about 100 nm.

Claim 13

A diode contact as in claim 1, wherein said silicon substrate has a dopant of the second type.

Claim 14

A diode contact as in claim 12, wherein said silicon substrate has a dopant concentration of 1×10 16 cm -3 .

Claim 15

An integrated polysilicon diode contact, comprising: a gate oxide layer deposited on a silicon substrate, said silicon substrate having a p-type dopant; a first highly doped layer having an n-type dopant deposited on said gate oxide layer; a source region formed in a surface of said silicon substrate, wherein said source region has an n-type dopant; a second highly doped layer having a p-type dopant deposited on said source region, said second highly doped layer being spaced from said gate oxide layer and said first highly doped layer; and a third lower doped layer having a p-type dopant deposited on and interconnecting said first highly doped layer and said second highly doped layer, said third lower doped layer forming a p-n junction with said source region.

Claim 16

An integrated polysilicon diode contact, comprising: a gate oxide layer deposited on a silicon substrate, said silicon substrate having a p-type dopant; a first highly doped layer having an n-type dopant deposited on said gate oxide layer; a source region formed in a surface of said silicon substrate, wherein said source region has an n-type dopant; a second highly doped layer having a p-type dopant deposited on said source region, said second highly doped layer being spaced from said gate oxide layer and said first highly doped layer; and a third lower doped layer having a p-type dopant deposited on and interconnecting said first highly doped layer and said second highly doped layer, said third lower doped layer forming a p-n junction with said source region.

Claim 17

An integrated polysilicon diode contact, comprising: a gate oxide layer deposited on a silicon substrate; a first highly doped layer having a dopant of a first type deposited on said gate oxide layer; a source region formed in a surface of said silicon substrate, wherein said source region has a dopant of the first type; a second highly doped layer having a dopant of a second different type deposited on said source region, said second highly doped layer being spaced from said gate oxide layer and said first highly doped layer; a dopant diffusion suppression layer deposited on said first highly doped layer and said second highly doped layer, said dopant diffusion suppression layer having a thickness of about 1-2 nm and being selected form the group consisting of an oxide layer and a polycide layer; and a third lower doped layer having a dopant of the second type deposited on said dopant diffusion suppression layer, said third lower doped layer interconnecting the first highly doped layer and said second highly doped layer, and said third lower doped layer forming a p-n junction with said source region.

Claim 18

An integrated polysilicon diode contact, comprising: a gate oxide layer deposited on a silicon substrate; a first highly doped layer having a dopant of a first type deposited on said gate oxide layer; a source region formed in a surface of said silicon substrate, wherein said source region has a dopant of the first type; a second highly doped layer having a dopant of a second different type deposited on said source region, said second highly doped layer being spaced from said gate oxide layer and said first highly doped layer; a dopant diffusion suppression layer deposited on said first highly doped layer and said second highly doped layer, said dopant diffusion suppression layer having a thickness of about 1-2 nm and being selected form the group consisting of an oxide layer and a polycide layer; and a third lower doped layer having a dopant of the second type deposited on said dopant diffusion suppression layer, said third lower doped layer interconnecting the first highly doped layer and said second highly doped layer, and said third lower doped layer forming a p-n junction with said source region.

Claim 19

A diode contact as in claim 15, wherein said dopant of said first type is an n-type dopant, and said dopant of said second type is a p-type dopant.

Claim 20

A diode contact as in claim 16, wherein said p-type dopant is selected from arsenic or phosphorus, and said n-type dopant is boron.

Claim 21

A diode contact as in claim 15, wherein said first highly doped layer is one of silicon and polysilicon.

Claim 22

A diode contact as in claim 15, wherein said second highly doped layer is one of silicon and polysilicon.

Claim 23

A diode contact as in claim 15, wherein said third lower doped layer is one of silicon and polysilicon.