Patent US5708303A successfully refreshed from Google Patents.
US5708303A
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Semiconductor device having damascene interconnects
Assignee: Texas Instruments Inc
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Filing: 1996-11-01
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Granted: 1998-01-13
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Expires: 2016-11-01
Abstract
Abstract This is a device and method of optimizing capacitance and performance for multilevel interconnects. The device comprising: a semiconductor layer 70; a first high-k layer 68 above the semiconductor layer; a first insulating layer 66 above the first high-k layer 68; an interconnect layer 58 above the first insulating layer 66; a second insulating layer 64 around the interconnect layer 58; and a second high-k layer 52 above the second insulating layer 64 and the interconnect layer 58. The device may have a low-k material inserted between closely spaced metal interconnects. Alternatively, the device may have air gaps between closely spaced metal interconnects. In addition, the first high-k layer may be used as an oxide etch stop.
Inventors
- 👤 Shin-puu Jeng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:26
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/48; H10W20/495
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
55 words
An interconnect structure in a semiconductor device comprising: a semiconductor layer; a first high-k layer above said semiconductor layer; a plurality of interconnects above said first high-k layer, with a first low-k material between said plurality of interconnects that are at a relatively close proximity; and a second high-k layer above said plurality of interconnects.
Claim 2
Dependent Claim
55 words
An interconnect structure in a semiconductor device comprising: a semiconductor layer; a first high-k layer above said semiconductor layer; a plurality of interconnects above said first high-k layer, with a first low-k material between said plurality of interconnects that are at a relatively close proximity; and a second high-k layer above said plurality of interconnects.
Claim 3
Dependent Claim
25 words
The device of claim 1, wherein said plurality of interconnects are comprised of a metal barrier layer, a metal layer and a metal cap layer.
Claim 4
Dependent Claim
14 words
The device of claim 1, wherein said plurality of interconnects are comprised of aluminum.
Claim 5
Dependent Claim
33 words
The device of claim 1, wherein said device includes an insulating layer between said first high-k layer and said plurality of interconnects, wherein said insulating layer is comprised of a second low-k material.
Claim 6
Dependent Claim
33 words
The device of claim 1, wherein said device includes an insulating layer between said plurality of interconnects and said second high-k layer, wherein said insulating layer is comprised of a second low-k material.
Claim 7
Dependent Claim
18 words
The device of claim 1, wherein said plurality of interconnects are comprised of a damascene processed metal material.
Claim 8
Dependent Claim
14 words
The device of claim 4, wherein said insulating layer is comprised of silicon dioxide.
Claim 9
Dependent Claim
14 words
The device of claim 5, wherein said insulating layer is comprised of silicon dioxide.
Claim 10
Dependent Claim
55 words
An interconnect structure in a semiconductor device comprising: a semiconductor layer; a first high-k layer above said semiconductor layer; a first insulating layer above said first high-k layer; and a plurality of interconnects above said first insulating layer with a first low-k material between said plurality of interconnects that are at a relatively close proximity.
Claim 11
Dependent Claim
55 words
An interconnect structure in a semiconductor device comprising: a semiconductor layer; a first high-k layer above said semiconductor layer; a first insulating layer above said first high-k layer; and a plurality of interconnects above said first insulating layer with a first low-k material between said plurality of interconnects that are at a relatively close proximity.
Claim 12
Dependent Claim
19 words
The device of claim 9, wherein said device further includes a second insulating layer above said plurality of interconnects.
Claim 13
Dependent Claim
19 words
The device of claim 10, wherein said device further includes a second high-k layer above said second insulating layer.
Claim 14
Dependent Claim
25 words
The device of claim 9, wherein said plurality of interconnects are comprised of a metal barrier layer, a metal layer and a metal cap layer.
Claim 15
Dependent Claim
14 words
The device of claim 9, wherein said plurality of interconnects are comprised of aluminum.
Claim 16
Dependent Claim
15 words
The device of claim 9, wherein said first insulating layer is comprised of silicon dioxide.
Claim 17
Dependent Claim
17 words
The device of claim 10, wherein said second insulating layer is comprised of a second low-k material.
Claim 18
Dependent Claim
18 words
The device of claim 9, wherein said plurality of interconnects are comprised of a damascene, processed metal material.
Claim 19
Dependent Claim
55 words
An interconnect structure in a semiconductor device comprising: a semiconductor layer; a plurality of interconnects above said semiconductor layer, with a first low-k material between said plurality of interconnects that are at a relatively close proximity; a first insulating layer around said plurality of interconnects; and a first high-k layer above said plurality of interconnects.
Claim 20
Dependent Claim
55 words
An interconnect structure in a semiconductor device comprising: a semiconductor layer; a plurality of interconnects above said semiconductor layer, with a first low-k material between said plurality of interconnects that are at a relatively close proximity; a first insulating layer around said plurality of interconnects; and a first high-k layer above said plurality of interconnects.
Claim 21
Dependent Claim
24 words
The device of claim 17, wherein said device further includes a second high-k layer above said semiconductor layer and below said plurality of interconnects.
Claim 22
Dependent Claim
24 words
The device of claim 18, wherein said device further includes a second insulating layer above said semiconductor layer and below said second high-k layer.
Claim 23
Dependent Claim
25 words
The device of claim 17, wherein said plurality of interconnects are comprised of a metal barrier layer, a metal layer and a metal cap layer.
Claim 24
Dependent Claim
14 words
The device of claim 17, wherein said plurality of interconnects are comprised of aluminum.
Claim 25
Dependent Claim
15 words
The device of claim 17, wherein said first insulating layer is comprised of silicon dioxide.
Claim 26
Dependent Claim
30 words
The device of claim 17, wherein said device includes a second insulating layer above said first high-k layer, wherein said second insulating layer is comprised of a second low-k material.
Claim 27
Dependent Claim
18 words
The device of claim 17, wherein said plurality of interconnects are comprised of a damascene processed metal material.
Claim 28
Dependent Claim
67 words
An interconnect structure in a semiconductor device comprising: a semiconductor layer; a first high-k layer above said semiconductor layer; a plurality of interconnects above said first high-k layer, with a first low-k material between said plurality of interconnects that are at a relatively close proximity; an insulating layer around said plurality of interconnects; and a second high-k layer above said insulating layer and said plurality of interconnects.
Claim 29
Dependent Claim
67 words
An interconnect structure in a semiconductor device comprising: a semiconductor layer; a first high-k layer above said semiconductor layer; a plurality of interconnects above said first high-k layer, with a first low-k material between said plurality of interconnects that are at a relatively close proximity; an insulating layer around said plurality of interconnects; and a second high-k layer above said insulating layer and said plurality of interconnects.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-01-12 | 2001-07-14 | 2002-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-12 | 2005-07-14 | 2006-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-12 | 2009-07-14 | 2010-01-13 | $7700.00 | Window Closed / Lapsed |