US5702870A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated-circuit via formation using gradient photolithography
Assignee: Philips Semiconductors Inc
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Filing: 1996-09-09
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Granted: 1997-12-30
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Expires: 2016-09-09
Abstract
Abstract A method of forming a metal interconnect structure for a CMOS integrated circuit provides for deposition of via metal prior to formation of an intermetal dielectric. After a submetal dielectric is deposited, lower metal and via metals are deposited. Gradient photolithography is used to define a via pattern and a lower metal pattern in a positive photoresist. After etching, the lower metal assumes the lower metal pattern and the via metal assumes the via pattern. A three-layer intermetal dielectric includes a spin-on glass sandwiched between two deposited silicon dioxide layers. The resulting structure is polished until at least some of the vias are exposed. Other vias can be exposed by via apertures that are define photolithographically. An upper metal layer is then deposited, filling the via apertures. The upper metal is then patterned to complete the interconnect structure. This method provides that via metal is insulated from spin-on glass moisture by the deposited oxide. Prior art problems with metal interconnect integrity due to misalignment, poor step coverage, and via poisoning are eliminated in some cases and reduced in others.
Inventors
- 👤 Hunter Barham Brugge
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 00:14
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
223 words
A method of forming a metal interconnect structure in an integrated circuit, said method comprising the steps of: depositing a lower metal layer over a submetal dielectric; depositing a via metal layer over said lower metal layer; applying positive photoresist over said via metal layer; exposing said photoresist so that a removal-pattern region of said photoresist is relatively heavily exposed, a via-pattern region of said photoresist is relatively lightly exposed, and a lower-pattern region of said photoresist is relatively moderately exposed; developing said photoresist; etching so as to remove said lower and via metal layers from said removal-pattern region, remove said via metal layer from said lower-pattern region while leaving at least some thickness of said lower metal layer in said lower-pattern region, and leaving at least some of said via metal layer in said via-pattern region; forming intermetal dielectric over the structure resulting from said etching; forming via openings through said dielectric to expose at least some of said via metal layer in said via-pattern region; depositing an upper metal layer on said intermetal dielectric so as to contact said via metal layer in said via-pattern region; and photolithographically patterning said upper metal layer to form a relief pattern therein; whereby said via metal layer constitutes at least part of a via between said lower metal layer and said upper metal layer.
Claim 2
Independent Claim
223 words
A method of forming a metal interconnect structure in an integrated circuit, said method comprising the steps of: depositing a lower metal layer over a submetal dielectric; depositing a via metal layer over said lower metal layer; applying positive photoresist over said via metal layer; exposing said photoresist so that a removal-pattern region of said photoresist is relatively heavily exposed, a via-pattern region of said photoresist is relatively lightly exposed, and a lower-pattern region of said photoresist is relatively moderately exposed; developing said photoresist; etching so as to remove said lower and via metal layers from said removal-pattern region, remove said via metal layer from said lower-pattern region while leaving at least some thickness of said lower metal layer in said lower-pattern region, and leaving at least some of said via metal layer in said via-pattern region; forming intermetal dielectric over the structure resulting from said etching; forming via openings through said dielectric to expose at least some of said via metal layer in said via-pattern region; depositing an upper metal layer on said intermetal dielectric so as to contact said via metal layer in said via-pattern region; and photolithographically patterning said upper metal layer to form a relief pattern therein; whereby said via metal layer constitutes at least part of a via between said lower metal layer and said upper metal layer.
Claim 3
Dependent Claim
36 words
A method as recited in claim 1 wherein said step of forming said intermetal dielectric involves: depositing a first oxide; spinning on glass over the structure resulting from said first oxide; and depositing a second oxide.
Claim 4
Dependent Claim
31 words
A method as recited in claim 2 wherein said step of forming said intermetal dielectric involves performing a blanket etch after spinning on said glass and before depositing said second oxide.
Claim 5
Independent Claim
322 words
A method of forming electrical connections among integrated circuit devices, said method comprising the steps of: depositing a retowable submetal dielectric; opening contact apertures in said submetal dielectric to expose active regions of said circuit devices; reflowing said submetal dielectric so as to round the edges of said contact apertures; depositing a lower metal layer by depositing a first etch-stop sublayer, depositing a lower-metal conductor sublayer, and depositing a second etch-stop sublayer; depositing a via metal layer by depositing a via conductor sublayer, and depositing a third etch-stop sublayer; applying positive photoresist over said third etch-stop sublayer; exposing said photoresist so that a removal-pattern region of said photoresist is relatively heavily exposed, a via-pattern region of said photoresist is relatively lightly exposed, and a lower-pattern region of said photoresist is relatively moderately exposed; developing said photoresist; etching so as to remove said lower and via metal layers from said removal-pattern region, remove said via metal layer from said lower-pattern region while leaving at least some thickness of said lower metal layer in said lower-pattern region, and leaving at least some of said via metal layer in said via-pattern region; forming an intermetal dielectric by depositing a first oxide, spinning on glass, blanket etching back the structure resulting from said spinning on glass, and depositing a second oxide; polishing until at least some of said via metal layer is exposed; opening via apertures through said intermetal dielectric to expose via metal layer not exposed by said polishing; depositing an upper metal layer by depositing an etch-stop metal sublayer, and depositing an upper-metal conductor sublayer; and photolithographically patterning said upper metal layer so as to form a relief pattern therein; whereby said via metal layer constitutes at least part of a via between said lower metal layer and said upper metal layer, and said upper metal layer constitutes at least part of a via between said lower metal layer and said upper metal layer.
Claim 6
Independent Claim
322 words
A method of forming electrical connections among integrated circuit devices, said method comprising the steps of: depositing a retowable submetal dielectric; opening contact apertures in said submetal dielectric to expose active regions of said circuit devices; reflowing said submetal dielectric so as to round the edges of said contact apertures; depositing a lower metal layer by depositing a first etch-stop sublayer, depositing a lower-metal conductor sublayer, and depositing a second etch-stop sublayer; depositing a via metal layer by depositing a via conductor sublayer, and depositing a third etch-stop sublayer; applying positive photoresist over said third etch-stop sublayer; exposing said photoresist so that a removal-pattern region of said photoresist is relatively heavily exposed, a via-pattern region of said photoresist is relatively lightly exposed, and a lower-pattern region of said photoresist is relatively moderately exposed; developing said photoresist; etching so as to remove said lower and via metal layers from said removal-pattern region, remove said via metal layer from said lower-pattern region while leaving at least some thickness of said lower metal layer in said lower-pattern region, and leaving at least some of said via metal layer in said via-pattern region; forming an intermetal dielectric by depositing a first oxide, spinning on glass, blanket etching back the structure resulting from said spinning on glass, and depositing a second oxide; polishing until at least some of said via metal layer is exposed; opening via apertures through said intermetal dielectric to expose via metal layer not exposed by said polishing; depositing an upper metal layer by depositing an etch-stop metal sublayer, and depositing an upper-metal conductor sublayer; and photolithographically patterning said upper metal layer so as to form a relief pattern therein; whereby said via metal layer constitutes at least part of a via between said lower metal layer and said upper metal layer, and said upper metal layer constitutes at least part of a via between said lower metal layer and said upper metal layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-29 | 2001-06-30 | 2001-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-29 | 2005-06-30 | 2005-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-29 | 2009-06-30 | 2009-12-30 | $7700.00 | Window Closed / Lapsed |