US5699314A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video random access memory device and method implementing independent two we nibble control
Assignee: Micron Technology Inc
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Filing: 1996-10-17
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Granted: 1997-12-16
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Expires: 2016-10-17
Abstract
Abstract The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.
Inventors
- 👤 Glen Hush
- 👤 Mike Seibert
- 👤 Jeff Mailloux
- 👤 Mark R. Thomann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:27
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G11C7/1015; G11C7/103; G11C7/1033; G11C7/1075
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
259 words
A monolithic memory chip having a plurality of memory storage cells, comprising: a) a first write control pin for accepting a first external write enable signal; b) a second write control pin for accepting a second external write enable signal; c) a first portion having a first fraction of said memory storage cells, said first portion divided into memory subarrays, each subarray addressable by a first address, wherein for said first address a corresponding cell in each said subarray of said first portion is selected; d) a second portion having a second fraction of said memory storage cells, said second portion divided into memory subarrays, each subarray addressable by a second address, wherein for said second address a corresponding cell in each said subarray of said second portion is selected; and e) a control unit in electrical communication with said first and said second write control pins, said control unit generating a first and a second internal write signal in response to said first and said second external write enable signals respectively, said first internal write signal controlling a first write function to said subarrays of said first portion and said second internal write signal controlling a second write function to said subarrays of said second portion, such that first electrical data is written to said subarrays of said first portion during said first write function and such that second electrical data is written to said subarrays of said second portion during said second write function, said first and said second write functions being independent one from the other.
Claim 2
Dependent Claim
259 words
A monolithic memory chip having a plurality of memory storage cells, comprising: a) a first write control pin for accepting a first external write enable signal; b) a second write control pin for accepting a second external write enable signal; c) a first portion having a first fraction of said memory storage cells, said first portion divided into memory subarrays, each subarray addressable by a first address, wherein for said first address a corresponding cell in each said subarray of said first portion is selected; d) a second portion having a second fraction of said memory storage cells, said second portion divided into memory subarrays, each subarray addressable by a second address, wherein for said second address a corresponding cell in each said subarray of said second portion is selected; and e) a control unit in electrical communication with said first and said second write control pins, said control unit generating a first and a second internal write signal in response to said first and said second external write enable signals respectively, said first internal write signal controlling a first write function to said subarrays of said first portion and said second internal write signal controlling a second write function to said subarrays of said second portion, such that first electrical data is written to said subarrays of said first portion during said first write function and such that second electrical data is written to said subarrays of said second portion during said second write function, said first and said second write functions being independent one from the other.
Claim 3
Dependent Claim
59 words
The monolithic memory chip as specified in claim 1, wherein said first portion comprises four subarrays and wherein said second portion comprises four subarrays, such that during said first write function a nibble of data is written to said memory chip and such that during said second write function a nibble of data is written to said memory chip.
Claim 4
Dependent Claim
226 words
A monolithic memory chip having a circuit for storing electrical data, the circuit comprising: a) a first plurality of first circuit portions, each said first circuit portion of said first plurality comprising a matrix of memory storage cells for storing the electrical data; b) a second plurality of second circuit portions, each said second circuit portion of said second plurality comprising a matrix of memory storage cells for storing the electrical data; c) a logic currently configured to generate a first and a second internal write signal, said logic controlling means responsive to a first and a second external write enable signal; d) an input port for accepting the electrical data for storage; and e) a write control unit coupled to receive said first and said second internal write signals to control the transfer of the electrical data from said input port to said first and said second pluralities of circuit portions, such that the electrical data is written to each of said first circuit portions of said first plurality during a first write operation when said first internal write signal is active and that the electrical data is written to each of said second circuit portions of said second plurality during a second write operation when said second internal write signal is active, said first and said second write operations occurring independently of one another.
Claim 5
Dependent Claim
226 words
A monolithic memory chip having a circuit for storing electrical data, the circuit comprising: a) a first plurality of first circuit portions, each said first circuit portion of said first plurality comprising a matrix of memory storage cells for storing the electrical data; b) a second plurality of second circuit portions, each said second circuit portion of said second plurality comprising a matrix of memory storage cells for storing the electrical data; c) a logic currently configured to generate a first and a second internal write signal, said logic controlling means responsive to a first and a second external write enable signal; d) an input port for accepting the electrical data for storage; and e) a write control unit coupled to receive said first and said second internal write signals to control the transfer of the electrical data from said input port to said first and said second pluralities of circuit portions, such that the electrical data is written to each of said first circuit portions of said first plurality during a first write operation when said first internal write signal is active and that the electrical data is written to each of said second circuit portions of said second plurality during a second write operation when said second internal write signal is active, said first and said second write operations occurring independently of one another.
Claim 6
Dependent Claim
34 words
The circuit of claim 3, wherein said first write operation is performed without masking of said second write operation, and wherein said second write operation is performed without masking of said first write operation.
Claim 7
Dependent Claim
65 words
The circuit of claim 3, wherein said first write operation is performed to said first plurality and a read operation is performed to said second plurality during one of a plurality of memory cycles, and wherein said second write operation is performed to said second plurality and a read operation is performed to said first plurality during one of said plurality of same memory cycles.
Claim 8
Dependent Claim
40 words
The circuit as specified in claim 3, further comprising: a) a first external write input pin for receiving said first external write enable signal; and b) a second external write input pin for receiving said second external write enable signal.
Claim 9
Dependent Claim
62 words
The circuit as specified in claim 3, wherein said first plurality has four circuit portions such that a first nibble of the electrical data is written to the chip during said first write operation, and wherein said second plurality has four circuit portions such that a second nibble of the electrical data is written to the chip during said second write operation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-15 | 2001-06-16 | 2001-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-15 | 2005-06-16 | 2005-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-15 | 2009-06-16 | 2009-12-16 | $7700.00 | Window Closed / Lapsed |