Memory device

Claim 2

A memory device having a plurality of bank memories, comprising: first circuit means for delivering a plurality of control signals to said bank memories and for delaying said delivery of control signals to lower a power consumption during operation of said memory device, said control signals for reading data and writing data from and into said bank memories, wherein said first circuit means includes a plurality of NAND gates, and second circuit means for selecting one of said bank memories or all of said bank memories for input of signals.

Claim 3

The memory device occurring according to claim 1 wherein said first circuit means includes a plurality of NAND gates.

Claim 4

The memory device according to claim 1 wherein said second circuit means includes a plurality of OR gates.

Claim 5

The memory device according to claim 3 wherein an all bank selecting signal is generated to activate each of said OR gates, and a bank selecting signal is generated to activate a selection OR gate.

Claim 6

The memory device according to claim 4 wherein said OR gates can deliver one of a bank selecting signal and said all bank selecting signal to said NAND gates which also receive said control signals.

Claim 7

A memory device for simultaneously sending read and write signals to a plurality of bank memories and for erasing data in an amount in excess of one byte, comprising: a plurality of NAND gates for receiving a plurality of control signals, said control signals including a row address strobe (RAS) signal, a column address strobe (CAS) signal, and a write enable (WE) signal, each NAND gate also for receiving one of a plurality of bank selecting signals and an all bank selecting signal, the number of NAND gates being at least equal to the number of said bank memories; a plurality of delaying circuits for delaying the delivery of said control signals to said NAND gates; and a plurality of OR gates for receiving said bank selecting signals and said all bank selecting signal to selectively access said control signals into said bank memories, said bank selecting signals for selecting a single bank array and said all bank selecting signal for selecting more than one bank memory.

Claim 8

A memory device for simultaneously sending read and write signals to a plurality of bank memories and for erasing data in an amount in excess of one byte, comprising: a plurality of NAND gates for receiving a plurality of control signals, said control signals including a row address strobe (RAS) signal, a column address strobe (CAS) signal, and a write enable (WE) signal, each NAND gate also for receiving one of a plurality of bank selecting signals and an all bank selecting signal, the number of NAND gates being at least equal to the number of said bank memories; a plurality of delaying circuits for delaying the delivery of said control signals to said NAND gates; and a plurality of OR gates for receiving said bank selecting signals and said all bank selecting signal to selectively access said control signals into said bank memories, said bank selecting signals for selecting a single bank array and said all bank selecting signal for selecting more than one bank memory.

Claim 9

The memory device according to claim 6 wherein said delaying circuits only delay the RAS signal and the CAS signal to said bank memories.

Claim 10

The memory device according to claim 7 wherein the number of OR gates is at least equal to the number of said bank memories.

Claim 11

A memory device having a plurality of bank memories to which common address lines and common data lines are respectively connected, and a bank-selecting means having a plurality of first circuits, respectively comprised of a plurality of NAND gates whose input signals are the corresponding bank-selecting signal and control signal, connected to respective bank memories, each first circuit providing the corresponding bank memory with control signals needed for writing data into the corresponding bank memory or reading data from the same on receipt of a bank-selecting signal designating the same, said memory device comprising: a plurality of second circuits connected to said first circuit respectively for delivering a signal substantially equivalent to said bank-selecting signal to all of said first circuits so as to simultaneously deliver said control signals to all of said bank memories.

Claim 12

A memory device having a plurality of bank memories to which common address lines and common data lines are respectively connected, and a bank-selecting means having a plurality of first circuits, respectively comprised of a plurality of NAND gates whose input signals are the corresponding bank-selecting signal and control signal, connected to respective bank memories, each first circuit providing the corresponding bank memory with control signals needed for writing data into the corresponding bank memory or reading data from the same on receipt of a bank-selecting signal designating the same, said memory device comprising: a plurality of second circuits connected to said first circuit respectively for delivering a signal substantially equivalent to said bank-selecting signal to all of said first circuits so as to simultaneously deliver said control signals to all of said bank memories.

Claim 13

A memory device having a plurality of bank memories to which common address lines and common data lines are respectively connected, and a bank-selecting means having a plurality of first circuits connected to respective bank memories, each first circuit providing the corresponding bank memory with control signals needed for writing data into the corresponding bank memory or reading data from the same on receipt of a bank-selecting signal designating the same, said memory device comprising: a plurality of second circuits connected to said first circuit respectively for delivering a signal substantially equivalent to said bank-selecting signal to all of said first circuits so as to simultaneously deliver said control signals to all of said bank memories, said second circuits respectively comprised of a plurality of OR gates whose input signals are said bank-selecting signal and said equivalent signal to said bank-selecting signal.

Claim 14

A memory device having a plurality of bank memories to which common address lines and common data lines are respectively connected, and a bank-selecting means having a plurality of first circuits connected to respective bank memories, each first circuit providing the corresponding bank memory with control signals needed for writing data into the corresponding bank memory or reading data from the same on receipt of a bank-selecting signal designating the same, said memory device comprising: a plurality of second circuits connected to said first circuit respectively for delivering a signal substantially equivalent to said bank-selecting signal to all of said first circuits so as to simultaneously deliver said control signals to all of said bank memories, said second circuits respectively comprised of a plurality of OR gates whose input signals are said bank-selecting signal and said equivalent signal to said bank-selecting signal.

Claim 15

A memory device having a plurality of bank memories to which common address lines and common data lines are respectively connected, and a bank-selecting means having a plurality of first circuits respectively connected to the bank memories, each first circuit comprising a gate whose input signals are a bank-selecting signal designating the corresponding bank memory and control signals needed for writing data into the corresponding bank memory or reading data from the same, said gate providing the corresponding bank memory with the control signals on receipt of the bank-selecting signal, said memory device comprising: a second circuit connected to said first circuits for simultaneously delivering a signal substantially equivalent to said bank-selecting signal to all of said first circuits so as to cause the first circuits to deliver said control signals to all of said bank memories, whereby common data is written into all of the bank memories through the common data lines.

Claim 16

A memory device having a plurality of bank memories to which common address lines and common data lines are respectively connected, and a bank-selecting means having a plurality of first circuits respectively connected to the bank memories, each first circuit comprising a gate whose input signals are a bank-selecting signal designating the corresponding bank memory and control signals needed for writing data into the corresponding bank memory or reading data from the same, said gate providing the corresponding bank memory with the control signals on receipt of the bank-selecting signal, said memory device comprising: a second circuit connected to said first circuits for simultaneously delivering a signal substantially equivalent to said bank-selecting signal to all of said first circuits so as to cause the first circuits to deliver said control signals to all of said bank memories, whereby common data is written into all of the bank memories through the common data lines.

Claim 17

The memory device according to claim 10, wherein said second circuit delivers the signal substantially equivalent to said bank-selecting signal when a specific data is provided to all of said bank memories through the common data lines, wherein writing said specific data erases contents of the bank memories.

Claim 18

A memory device having a plurality of bank memories to which common address lines and common data lines are respectively connected, and a bank-selecting means having a plurality of first circuits respectively connected to the bank memories, each first circuit comprising a gate whose input signals are a bank-selecting signal designating the corresponding bank memory and control signals needed for writing data into the corresponding bank memory or reading data from the same, said gate providing the corresponding bank memory with the control signals on receipt of the bank-selecting signal, said memory device comprising: a second circuit connected to said first circuits for simultaneously delivering a signal substantially equivalent to said bank-selecting signal to all of said first circuits so as to cause the first circuits to deliver said control signals to all of said bank memories, and one or more of said first circuits comprising a delay circuit which temporarily delays the delivery of said control signals to the corresponding bank memories so as to prevent the control signals from being supplied simultaneously to all of the bank memories.

Claim 19

A memory device having a plurality of bank memories to which common address lines and common data lines are respectively connected, and a bank-selecting means having a plurality of first circuits respectively connected to the bank memories, each first circuit comprising a gate whose input signals are a bank-selecting signal designating the corresponding bank memory and control signals needed for writing data into the corresponding bank memory or reading data from the same, said gate providing the corresponding bank memory with the control signals on receipt of the bank-selecting signal, said memory device comprising: a second circuit connected to said first circuits for simultaneously delivering a signal substantially equivalent to said bank-selecting signal to all of said first circuits so as to cause the first circuits to deliver said control signals to all of said bank memories, and one or more of said first circuits comprising a delay circuit which temporarily delays the delivery of said control signals to the corresponding bank memories so as to prevent the control signals from being supplied simultaneously to all of the bank memories.

Claim 20

A memory device having a plurality of bank memories to which common address lines and common data lines are respectively connected, the memory device comprising: a plurality of gating means respectively connected to the bank memories, each gating means being provided with a bank-selecting signal designating the corresponding bank memory and control signals needed for writing data into the corresponding bank memory or reading data from the same, and providing the corresponding bank memory with the control signals on receipt of the bank-selecting signals; selecting means for selecting providing one of the gating means with the bank-selecting signal; all-bank-selecting means for providing all of said bank memories with the control signal on receipt of an all-bank-selecting signal, and means for providing all-bank-selecting means with the all-bank-selecting signal when a specific data is provided to all of the bank memories through the common data lines, wherein writing said specific data erases contents of the bank memories.

Claim 21

A memory device having a plurality of bank memories to which common address lines and common data lines are respectively connected, the memory device comprising: a plurality of gating means respectively connected to the bank memories, each gating means being provided with a bank-selecting signal designating the corresponding bank memory and control signals needed for writing data into the corresponding bank memory or reading data from the same, and providing the corresponding bank memory with the control signals on receipt of the bank-selecting signals; selecting means for selecting providing one of the gating means with the bank-selecting signal; all-bank-selecting means for providing all of said bank memories with the control signal on receipt of an all-bank-selecting signal, and means for providing all-bank-selecting means with the all-bank-selecting signal when a specific data is provided to all of the bank memories through the common data lines, wherein writing said specific data erases contents of the bank memories.

Claim 22

The memory device according to claim 14, wherein said gating means respectively comprise NAND gates.

Claim 23

The memory device according to claim 14 further comprising a delay means for temporarily delaying the delivery of said control signals to one or more bank memories to as to prevent the control signals from being supplied simultaneously to all of the bank memories.